Patents by Inventor Jang Sik Lee
Jang Sik Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128123Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.Type: ApplicationFiled: December 18, 2023Publication date: April 18, 2024Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jin Won JEONG, Jang Hee LEE, Young Hun JUN, Jong Woon LEE, Jae Sik CHOI
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Patent number: 11925129Abstract: The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.Type: GrantFiled: November 9, 2021Date of Patent: March 5, 2024Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Jang Sik Lee, Kwang Hyun Kim, Young Jun Park
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Publication number: 20220367809Abstract: The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.Type: ApplicationFiled: November 9, 2021Publication date: November 17, 2022Inventors: Jang Sik LEE, Kwang Hyun KIM, Young Jun PARK
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Publication number: 20220181353Abstract: A method for manufacturing a semiconductor memory device according to the inventive concept includes forming an electrode structure by alternately stacking insulation layers and electrodes on a substrate, forming a channel hole penetrating the electrode structure, and forming a vertical channel structure filling the channel hole, wherein the forming the vertical channel structure includes forming a ferroelectric layer on an inner sidewall of the channel hole, forming an oxide semiconductor layer on the ferroelectric layer, and performing an annealing process on the oxide semiconductor layer.Type: ApplicationFiled: November 18, 2021Publication date: June 9, 2022Applicant: Postech Research and Business Development FoundationInventors: Jang-Sik LEE, Ik-Jyae KIM, Min-Kyu KIM
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Patent number: 8268711Abstract: Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.Type: GrantFiled: June 1, 2010Date of Patent: September 18, 2012Assignee: Kookmin University Industry Academy Cooperation FoundationInventors: Jang-Sik Lee, Jinhan Cho, Jaegab Lee
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Patent number: 8237199Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.Type: GrantFiled: August 5, 2010Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Jung-Dal Choi, Chang-Seok Kang, Chang-Hyun Lee, Jang-Sik Lee, Vie-Na Kim
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Publication number: 20120138905Abstract: Provided are a flexible organic memory device and a method of manufacturing the same. The flexible organic memory device comprises a flexible substrate. A control gate electrode is disposed on the flexible substrate. A blocking organic insulating layer is disposed on the control gate electrode. A charge trapping layer is disposed on the blocking organic insulating layer, and includes a plurality of nanoparticles. A tunneling organic insulating layer is disposed on the charge trapping layer. An organic semiconductor layer is disposed on the tunneling organic insulating layer.Type: ApplicationFiled: June 20, 2011Publication date: June 7, 2012Applicant: Kookmin University Industry Academy Cooperation FoundationInventors: Jang-Sik LEE, Soo-Jin Kim
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Patent number: 7897458Abstract: Provided is a method of forming a floating gate, a non-volatile memory device using the same, and a method of fabricating the non-volatile memory device, in which nano-crystals of nano-size whose density and size can be easily adjusted, are synthesized using micelles so as to be used as the floating gate of the non-volatile memory device. The floating gate is fabricated by forming a tunnel oxide film on the semiconductor substrate, coating a gate formation solution on the tunnel oxide film in which the gate formation solution includes micelle templates into which precursors capable of synthesizing metallic salts in nano-structures formed by a self-assembly method are introduced, and arranging the metallic salts on the tunnel oxide film by removing the micelle templates, to thereby form the floating gate.Type: GrantFiled: March 25, 2008Date of Patent: March 1, 2011Assignee: Kookmin University Industry Academy Cooperation FoundationInventors: Jaegab Lee, Jang-Sik Lee, Chi Young Lee, Byeong Hyeok Sohn
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Publication number: 20100317157Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.Type: ApplicationFiled: August 5, 2010Publication date: December 16, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Sun Sel, Jung-Dal Choi, Chang-Seok Kang, Chang-Hyun Lee, Jang-Sik Lee, Vie-Na Kim
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Publication number: 20100276747Abstract: Provided is a charge trapping layer which has excellent memory characteristics, a method of forming the charge trapping layer, a nonvolatile memory device using the charge trapping layer, and a method of fabricating the nonvolatile memory device, in which a hybrid nanoparticle which is obtained by mixing a nanoparticle having an excellent programming characteristic with a nanoparticle having an excellent erasing characteristic is used as the charge trapping layer. The charge trapping layer for use in the nanoparticle is discontinuously formed between a tunneling oxide film and a control oxide film, and includes at least two different kinds of numerous nanoparticles.Type: ApplicationFiled: October 30, 2009Publication date: November 4, 2010Inventors: Jang-Sik Lee, Byeong Hyeok Sohn, Yong Mu Kim, Jeong Hwa Kwon, Hyunjung Shin, Jaegab Lee
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Publication number: 20100240208Abstract: Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventors: JANG-SIK LEE, JINHAN CHO, JAEGAB LEE
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Patent number: 7795643Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.Type: GrantFiled: August 22, 2006Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Sun Sel, Jung-Dal Choi, Chang-Seok Kang, Chang-Hyun Lee, Jang-Sik Lee, Vie-Na Kim
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Patent number: 7745874Abstract: Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of nano size is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-crystal film which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of metal nano-crystals for trapping charges are deposited. The floating gate is made by self-assembling the metal nano-crystals on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.Type: GrantFiled: October 16, 2007Date of Patent: June 29, 2010Assignee: Kookmin University Industry Academy Cooperation FoundationInventors: Jang-Sik Lee, Jinhan Cho, Jaegab Lee
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Publication number: 20090085094Abstract: Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of nano size is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-crystal film which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of metal nano-crystals for trapping charges are deposited. The floating gate is made by self-assembling the metal nano-crystals on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.Type: ApplicationFiled: October 16, 2007Publication date: April 2, 2009Inventors: Jang-Sik Lee, Jinhan Cho, Jaegab Lee
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Publication number: 20080237692Abstract: Provided is a method of forming a floating gate, a non-volatile memory device using the same, and a method of fabricating the non-volatile memory device, in which nano-crystals of nano-size whose density and size can be easily adjusted, are synthesized using micelles so as to be used as the floating gate of the non-volatile memory device. The floating gate is fabricated by forming a tunnel oxide film on the semiconductor substrate, coating a gate formation solution on the tunnel oxide film in which the gate formation solution includes micelle templates into which precursors capable of synthesizing metallic salts in nano-structures formed by a self-assembly method are introduced, and arranging the metallic salts on the tunnel oxide film by removing the micelle templates, to thereby form the floating gate.Type: ApplicationFiled: March 25, 2008Publication date: October 2, 2008Inventors: Jaegab LEE, Jang-Sik LEE, Chi Young LEE, Byeong Hyeok SOHN
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Publication number: 20070104011Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.Type: ApplicationFiled: August 22, 2006Publication date: May 10, 2007Inventors: Jong-Sun Sel, Jung-Dal Choi, Chang-Seok Kang, Chang-Hyun Lee, Jang-Sik Lee, Vie-Na Kim
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Patent number: 6635571Abstract: Disclosed is a process for depositing an aluminum oxide thin film necessary for semiconductor devices. The process includes the steps of: subjecting a gaseous organoaluminum compound as an aluminum source in contact with a target substrate and depositing aluminum using plasma. The steps are sequentially repeated to form an aluminum thin film, and further includes the step of oxidizing the aluminum thin film using oxygen plasma. This deposition cycle is repeated to obtain an aluminum oxide thin film. The present invention uses an aluminum source containing less contaminant compared to the prior art, thus obtaining aluminum oxide of high quality. Furthermore, the temperature of the gas supply and the reactor can be lowered in relation to the prior art method to reduce costs in the fabrication of semiconductor devices.Type: GrantFiled: April 25, 2001Date of Patent: October 21, 2003Inventors: Seung Ki Joo, Jang Sik Lee, Chang Wook Jeong
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Publication number: 20020081394Abstract: Disclosed is a process for depositing an aluminum oxide thin film necessary for semiconductor devices. The process includes the steps of: subjecting a gaseous organoaluminum compound as an aluminum source in contact with a target substrate and depositing aluminum using plasma, which steps are sequentially repeated to form an aluminum thin film, and further the step of oxidizing the aluminum thin film using oxygen plasma. This deposition cycle is repeated to obtain an aluminum oxide thin film.Type: ApplicationFiled: April 25, 2001Publication date: June 27, 2002Inventors: Seung Ki Joo, Jang Sik Lee, Chang Wook Jeong
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Patent number: 6340600Abstract: A method for fabricating a large single-grained ferroelectric thin film grown by selectively nucleated lateral crystallization (SNLC) using an artificial nucleation seed, a method for fabricating a ferroelectric capacitor using the same, and a method for fabricating a ferroelectric memory device using the same. The ferroelectric thin film fabrication method includes the steps of forming a first conductive layer on one side of a semiconductor substrate, by using a conductive material, forming an artificial nucleation seed in an island form adjacent a position where a ferroelectric thin film is to be formed in the upper portion of the first conductive layer, forming a ferroelectric thin film on the whole surface of the substrate including the nucleation seed, and thermally annealing the ferroelectric thin film to thereby grow the ferroelectric thin film positioned in the lateral side of the nucleation seed into a single-grained ferroelectric thin film.Type: GrantFiled: April 19, 2001Date of Patent: January 22, 2002Assignee: Seung Kee JooInventors: Seung Ki Joo, Jang Sik Lee
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Patent number: 6335207Abstract: A method for fabricating a ferroelectric thin film, capable of preventing degradation due to fatigue and aging of a ferroelectric thin film of PZT and enabling crystallization at a low temperature. The ferroelectric thin film fabrication method includes the steps of forming an insulation layer on one side of a semiconductor substrate, forming an electrode layer on the insulation layer, forming a ferroelectric layer on the electrode layer, and performing an ion damage processing on the ferroelectric layer using an ionized gas.Type: GrantFiled: December 28, 2000Date of Patent: January 1, 2002Inventors: Seung Ki Joo, Jang Sik Lee, Eung Chul Park