Patents by Inventor Jang-Soo Lee
Jang-Soo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955287Abstract: A multilayer electronic component includes: a body including an active portion including internal electrodes disposed alternately with dielectric layers and cover portions disposed on upper and lower surfaces of the active portion; and external electrodes including an electrode layer disposed on the body, and an average thickness of the cover portion is 14 to 17 ?m and a maximum thickness of the electrode layer is 5 to 20 ?m.Type: GrantFiled: December 8, 2021Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jang Yeol Lee, Hye Min Bang, Bum Soo Kim
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Publication number: 20240083767Abstract: A precursor for a positive electrode active material and a method of making the same are disclosed herein. In some embodiments a method includes forming precursor seeds for a positive electrode active material by a co-precipitation reaction while supplying a transition metal aqueous solution, an ammonium cationic complexing agent, and a basic compound to a reaction solution, and growing precursor particles for a positive electrode active material by a co-precipitation reaction while supplying a transition metal aqueous solution, an ammonium cationic complexing agent, and a basic compound to the reaction solution containing the precursor seeds, wherein the co-precipitation reaction to grow the precursor particles proceeds while continuously increasing feed rates of the transition metal aqueous solution and the ammonium cationic complexing agent.Type: ApplicationFiled: February 18, 2022Publication date: March 14, 2024Applicant: LG Chem, Ltd.Inventors: Min Joon Lee, Seong Ji Ye, Seung Beom Cho, Jang Soo Lee, Yoon Bin Park
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Patent number: 11907724Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.Type: GrantFiled: February 4, 2022Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Lior Binyamini, Chung-Lung K. Shum, Ludmila Zernakov, Markus Kaltenbach, Jang-Soo Lee
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Patent number: 11797446Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.Type: GrantFiled: October 29, 2021Date of Patent: October 24, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent Abali, Alper Buyuktosunoglu, Brian Robert Prasky, Jang-Soo Lee, Deanna Postles Dunn Berger
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Publication number: 20230251864Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.Type: ApplicationFiled: February 4, 2022Publication date: August 10, 2023Inventors: Lior Binyamini, Chung-Lung K. Shum, Ludmila Zernakov, Markus Kaltenbach, Jang-Soo Lee
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Publication number: 20230133372Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bulent ABALI, Alper BUYUKTOSUNOGLU, Brian Robert PRASKY, Jang-Soo LEE, Deanna Postles Dunn BERGER
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Patent number: 11243774Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, Jr., Jonathan Hsieh
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Patent number: 11175923Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.Type: GrantFiled: February 13, 2017Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, James J. Bonanno, Adam B. Collura, Bruce C. Giamei, Christian Jacobi, Jang-Soo Lee, Edward T. Malley, Lawrence J. Powell, Jr., Anthony Saporito
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Patent number: 11113055Abstract: A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.Type: GrantFiled: March 19, 2019Date of Patent: September 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Malley, Jang-Soo Lee, Anthony Saporito, Chung-Lung K. Shum, Gregory William Alexander
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Publication number: 20210245054Abstract: A method for providing a game or test application can include causing a workplace to be displayed on an interface, the workplace comprising a plurality of field objects and a plurality of mechanic objects, wherein each of the mechanic objects is positioned within a field object; causing a plurality of controllable objects to be displayed on the interface; receiving a command to move one of the controllable objects to a position that overlays at least a portion of the plurality of field objects; converting the overlaid portion of the plurality of field objects to an active region; identifying a mechanic object contained within the active region; and in response to identifying the mechanic object contained within the active region, running a mechanic object behavior on the mechanic object within the active region.Type: ApplicationFiled: February 8, 2021Publication date: August 12, 2021Applicant: YISIA Games LtdInventors: Yisia Young Suk Lee, Jang Soo Lee
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Patent number: 10977040Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: GrantFiled: February 19, 2019Date of Patent: April 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
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Patent number: 10929142Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Patent number: 10824426Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: GrantFiled: April 12, 2019Date of Patent: November 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
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Publication number: 20200301710Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Publication number: 20200301711Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: James Raymond Cuffney, Adam Collura, JAMES BONANNO, Edward Malley, Anthony Saporito, Jang-Soo Lee, Michael Cadigan, JR., Jonathan Hsieh
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Publication number: 20200301706Abstract: A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Inventors: Edward Malley, Jang-Soo Lee, Anthony Saporito, Chung-Lung K. Shum, Gregory William Alexander
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Publication number: 20200264882Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: ApplicationFiled: February 19, 2019Publication date: August 20, 2020Inventors: JAMES RAYMOND CUFFNEY, ADAM COLLURA, JAMES BONANNO, JANG-SOO LEE, EYAL NAOR, YAIR FRIED, BRIAN ROBERT PRASKY
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Patent number: 10496405Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: GrantFiled: November 20, 2017Date of Patent: December 3, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
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Publication number: 20190235864Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: ApplicationFiled: April 12, 2019Publication date: August 1, 2019Inventors: JANE H. BARTIK, CHRISTIAN JACOBI, DAVID LEE, JANG-SOO LEE, ANTHONY SAPORITO, CHRISTIAN ZOELLIN
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Patent number: 10331446Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: GrantFiled: May 23, 2017Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin