Abstract: A circuit for driving a liquid crystal display includes a high selection unit turned on by a high selection signal, a low selection unit turned on by a low selection signal and transferring a low data signal to one side of the first storage capacitor, a high transfer unit connected to one side of the first storage capacitor, turned on by a high transfer signal and transferring voltage, a low transfer unit connected to one side of the first storage capacitor, turned on by a low transfer signal and transferring the voltage stored at one side of the first storage capacitor to one side of the liquid crystal capacitor, and a reset unit connected to one side of the liquid crystal capacitor, turned on by a reset signal and transferring a center voltage to one side of the liquid crystal capacitor.

Abstract: A circuit for driving a liquid crystal display includes: a high selection unit turned on by a high selection signal and transferring a high data signal or a common voltage to one side of a storage capacitor; a low selection unit; a high transfer unit connected to one side of the storage capacitor; and a low transfer unit connected to the other side of the storage capacitor, turned on by a low transfer signal and transferring voltage stored at the other side of the storage capacitor to one side of the liquid crystal capacitor or transferring the low data signal or the common voltage transferred by the low selection unit to one side of the liquid crystal capacitor.

Abstract: A circuit for driving a liquid crystal display includes: a high selection unit turned on by a high selection signal and transferring a high data signal or a common voltage to one side of a storage capacitor; a low selection unit; a high transfer unit connected to one side of the storage capacitor; and a low transfer unit connected to the other side of the storage capacitor, turned on by a low transfer signal and transferring voltage stored at the other side of the storage capacitor to one side of the liquid crystal capacitor or transferring the low data signal or the common voltage transferred by the low selection unit to one side of the liquid crystal capacitor.

Abstract: A circuit for driving a liquid crystal display includes: a high selection unit turned on by a high selection signal; a low selection unit turned on by a low selection signal and transferring a low data signal to one side of the first storage capacitor; a high transfer unit connected to one side of the first storage capacitor, turned on by a high transfer signal and transferring voltage; a low transfer unit connected to one side of the first storage capacitor, turned on by a low transfer signal and transferring the voltage stored at one side of the first storage capacitor to one side of the liquid crystal capacitor; and a reset unit connected to one side of the liquid crystal capacitor, turned on by a reset signal and transferring a center voltage to one side of the liquid crystal capacitor.

Abstract: A circuit for driving a liquid crystal display includes: a high selection unit turned on by a high selection signal and transferring a high data signal or a common voltage to one side of a storage capacitor; a low selection unit; a high transfer unit connected to one side of the storage capacitor; and a low transfer unit connected to the other side of the storage capacitor, turned on by a low transfer signal and transferring voltage stored at the other side of the storage capacitor to one side of the liquid crystal capacitor or transferring the low data signal or the common voltage transferred by the low selection unit to one side of the liquid crystal capacitor.

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers invert the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers inverters the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Abstract: An improved address transition detection circuit prevents malfunctions of a memory by generating an address transition detection signal having a certain pulse width regardless of the width of a pulse of an address signal inputted to a memory. The circuit includes a NOR-gate for NORing an address signal and a chip selection signal, which are externally applied thereto. A level maintaining unit maintains a level of a signal outputted from the NOR-gate for a predetermined time, in accordance with first and second latch signals and first and second delay signals, to output first and second level maintaining signals of different levels. A latch latches the first and second level maintaining signals outputted from the level maintaining unit and outputs first and second latch signals. First and second signal delay units delay first and second latch signals outputted from the latch for a predetermined time and output first and second delay signals.