Patents by Inventor Jang Syun Ming

Jang Syun Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shallow trench isolation method for reducing oxide thickness variations at different pattern densities
    Patent number: 7098116
    Abstract: A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: August 29, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Cheng Lu, Chuan-Ping Hou, Chu-Yun Fu, Chang Wen, Jang Syun Ming