Abstract: A polysilicon layer including a channel region, and a source region and a drain region located on opposite sides of the channel region is formed on a lower insulating substrate. A gate wire including a plurality of gate lines and a plurality of gate electrodes, which are branched from the gate lines and overlap the channel region, and a storage wire including a plurality of storage electrodes and storage lines connected to the storage electrodes and parallel to the gate lines are formed on the gate insulating layer covering the polysilicon layer. Furthermore, a plurality of first insulating layers covering the gate wire and the storage wire are formed on the gate insulating layers. The first insulating layer has the same shape as the gate insulating layer and is formed extending to the gate wire and the storage wire.

Abstract: A polysilicon layer including a channel region, and a source region and a drain region located on opposite sides of the channel region is formed on a lower insulating substrate. A gate wire including a plurality of gate lines and a plurality of gate electrodes, which are branched from the gate lines and overlap the channel region, and a storage wire including a plurality of storage electrodes and storage lines connected to the storage electrodes and parallel to the gate lines are formed on the gate insulating layer covering the polysilicon layer. Furthermore, a plurality of first insulating layers covering the gate wire and the storage wire are formed on the gate insulating layers. The first insulating layer has the same shape as the gate insulating layer and is formed extending to the gate wire and the storage wire.