Patents by Inventor Jang-Woo Ryu
Jang-Woo Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135985Abstract: A semiconductor device includes a chip select signal flip-flop configured to: latch a chip select signal in-sync with a first propagation clock signal, and output a first chip select enable signal, and latch the chip select signal in-sync with a second propagation clock signal having a phase opposite to a phase of the first propagation clock signal, and output a second chip select enable signal; and a clock control circuit configured to generate the first propagation clock signal and the second propagation clock signal based on a clock signal, and selectively output one of the first propagation clock signal and the second propagation clock signal based on an enable level of the first chip select enable signal and an enable level of the second chip select enable signal.Type: ApplicationFiled: April 9, 2023Publication date: April 25, 2024Inventors: Seunghwan Hong, Jang-Woo Ryu
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Publication number: 20230368824Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.Type: ApplicationFiled: November 7, 2022Publication date: November 16, 2023Inventors: Sanguk Lee, Daehyun Kwon, Jang-Woo Ryu, Hangi Jung
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Patent number: 11626185Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: GrantFiled: April 18, 2022Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
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Publication number: 20220238178Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Inventors: Kyung-Ryun KIM, Yoon-Na OH, Hyung-Jin KIM, Hui-Kap YANG, Jang-Woo RYU
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Patent number: 11335431Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: GrantFiled: March 29, 2021Date of Patent: May 17, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
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Patent number: 11189333Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.Type: GrantFiled: July 26, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Woo Ryu, Soojung Rho
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Patent number: 11159149Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.Type: GrantFiled: September 15, 2020Date of Patent: October 26, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Soojung Rho, Jang-Woo Ryu, Hyunah An, Hangi Jung
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Publication number: 20210233604Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: ApplicationFiled: March 29, 2021Publication date: July 29, 2021Inventors: Kyung-Ryun KIM, Yoon-Na OH, Hyung-Jin KIM, Hui-Kap YANG, Jang-Woo RYU
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Publication number: 20210226617Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.Type: ApplicationFiled: September 15, 2020Publication date: July 22, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Soojung RHO, Jang-Woo RYU, Hyunah AN, Hangi JUNG
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Publication number: 20210183427Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.Type: ApplicationFiled: July 26, 2020Publication date: June 17, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: JANG-WOO RYU, SOOJUNG RHO
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Patent number: 10971247Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: GrantFiled: February 22, 2019Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
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Patent number: 10553273Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.Type: GrantFiled: July 11, 2018Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Woo Ryu, Kyungryun Kim, Soo Hwan Kim, Huikap Yang
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Publication number: 20190304565Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.Type: ApplicationFiled: February 22, 2019Publication date: October 3, 2019Inventors: Kyung-Ryun KIM, Yoon-Na OH, Hyung-Jin KIM, Hui-Kap YANG, Jang-Woo RYU
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Patent number: 10318469Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.Type: GrantFiled: February 12, 2015Date of Patent: June 11, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Soo Jang, Gong-Heum Han, Chul-Sung Park, Jang-Woo Ryu, Chang-Yong Lee, Tae-Seong Jang
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Publication number: 20190139594Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.Type: ApplicationFiled: July 11, 2018Publication date: May 9, 2019Inventors: Jang-Woo RYU, KYUNGRYUN KIM, SOO HWAN KIM, HUIKAP YANG
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Patent number: 9588840Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.Type: GrantFiled: March 26, 2014Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hoi-ju Chung, Chul-sung Park, Tae-young Oh, Jang-woo Ryu, Chan-yong Lee, Tae-seong Jang, Gong-heum Han
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Patent number: 9164834Abstract: In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.Type: GrantFiled: January 22, 2014Date of Patent: October 20, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hoi-ju Chung, Chul-sung Park, Jae-Wook Lee, Jang-Woo Ryu, Tae-seong Jang, Gong-heum Han
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Publication number: 20150242352Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.Type: ApplicationFiled: February 12, 2015Publication date: August 27, 2015Inventors: MIN-SOO JANG, GONG-HEUM HAN, CHUL-SUNG PARK, JANG-WOO RYU, CHANG-YONG LEE, TAE-SEONG JANG
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Patent number: 9099196Abstract: A method of operating a semiconductor memory device is disclosed. The method may include receiving an access command, applying a first voltage to a selected word line of the semiconductor memory device for a period of time in response to receiving the access command, applying a second voltage to word lines adjacent to the selected word line before and after the period of time, and applying a third voltage to the word lines adjacent to the selected word line for the period of time, a voltage level of the third voltage greater than the second voltage. The applying the third voltage may occur when the semiconductor memory device is operated at a temperature below the predetermined temperature.Type: GrantFiled: December 26, 2013Date of Patent: August 4, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Woo Ryu, Young-Dae Lee
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Publication number: 20140331006Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.Type: ApplicationFiled: March 13, 2014Publication date: November 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hoi-Ju CHUNG, Chul-Sung PARK, Tae-Seong JANG, Gong-Heum HAN, Jang-Woo RYU