Patents by Inventor Jang-Seok Choi
Jang-Seok Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955124Abstract: An example electronic device includes a housing; a touchscreen display; a microphone; at least one speaker; a button disposed on a portion of the housing or set to be displayed on the touchscreen display; a wireless communication circuit; a processor; and a memory. When a user interface is not displayed on the touchscreen display, the electronic device enables a user to receive a user input through the button, receives user speech through the microphone, and then provides data on the user speech to an external server. An instruction for performing a task is received from the server. When the user interface is displayed on the touchscreen display, the electronic device enables the user to receive the user input through the button, receives user speech through the microphone, and then provides data on the user speech to the external server.Type: GrantFiled: January 10, 2022Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Ki Kang, Jang-Seok Seo, Kook-Tae Choi, Hyun-Woo Kang, Jin-Yeol Kim, Chae-Hwan Li, Kyung-Tae Kim, Dong-Ho Jang, Min-Kyung Hwang
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Patent number: 11688453Abstract: A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device.Type: GrantFiled: October 13, 2021Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Taek Woon Kim, Jang Seok Choi
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Publication number: 20220246201Abstract: A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device.Type: ApplicationFiled: October 13, 2021Publication date: August 4, 2022Inventors: TAEK WOON KIM, JANG SEOK CHOI
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Publication number: 20220230688Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Yoo-jung Lee, Jang-seok CHOI, Duk-sung KIM, Hyun-joong KIM
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Patent number: 10867690Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.Type: GrantFiled: April 24, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Joong Kim, Duk-Sung Kim, Yoo-Jung Lee, Jang-Seok Choi
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Patent number: 10725672Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.Type: GrantFiled: December 31, 2018Date of Patent: July 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-young Lim, Young-jin Cho, Jang-seok Choi
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Publication number: 20200176062Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.Type: ApplicationFiled: August 1, 2019Publication date: June 4, 2020Inventors: Yoo-jung LEE, Jang-seok CHOI, Duk-sung KIM, Hyun-joong KIM
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Publication number: 20200135292Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.Type: ApplicationFiled: April 24, 2019Publication date: April 30, 2020Inventors: Hyun-Joong KIM, Duk-Sung KIM, Yoo-Jung LEE, Jang-Seok CHOI
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Publication number: 20190138230Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.Type: ApplicationFiled: December 31, 2018Publication date: May 9, 2019Inventors: Sun-young Lim, Young-jin Cho, Jang-seok Choi
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Patent number: 10169126Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.Type: GrantFiled: August 28, 2017Date of Patent: January 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-young Lim, Young-jin Cho, Jang-seok Choi
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Publication number: 20180101424Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.Type: ApplicationFiled: August 28, 2017Publication date: April 12, 2018Inventors: Sun-young Lim, Young-jin Cho, Jang-seok Choi
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Patent number: 9183890Abstract: The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller.Type: GrantFiled: January 4, 2012Date of Patent: November 10, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Seok Choi, Ju-Yun Jung
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Patent number: 8861159Abstract: The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.Type: GrantFiled: September 7, 2011Date of Patent: October 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Jin Lee, Jang Seok Choi
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Patent number: 8817571Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling command, the filling command determiner connects a first source voltage to a bitline and connects a second source voltage to a complementary bitline corresponding to the bitline. The bitline is connected to a selected memory cell corresponding to the address signal.Type: GrantFiled: May 12, 2011Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-seok Choi, Yong-hoon Kang
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Patent number: 8725976Abstract: In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state.Type: GrantFiled: January 3, 2011Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Beom-Sig Cho, Jang-Seok Choi
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Patent number: 8710655Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.Type: GrantFiled: July 11, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
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Publication number: 20130161812Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.Type: ApplicationFiled: July 11, 2012Publication date: June 27, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
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Patent number: 8369123Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.Type: GrantFiled: June 28, 2012Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Uk-Song Kang, Hoe-Ju Chung, Jang-Seok Choi, Hoon Lee
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Patent number: 8325551Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory banks. The semiconductor memory device performs refresh operations on the memory cell array using a normal refresh operation mode and a self-refresh operation mode. In the normal refresh operation mode, the semiconductor memory device performs refresh operations using an external high power supply voltage, and in the self-refresh operation mode, the semiconductor memory device performs refresh operations using an internal high power supply voltage. In the self-refresh operation mode, the refresh operations are performed in units of memory banks or memory bank groups.Type: GrantFiled: December 2, 2010Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Jang Seok Choi
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Publication number: 20120300528Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.Type: ApplicationFiled: June 28, 2012Publication date: November 29, 2012Inventors: Uk-song Kang, Hoe-Ju Chung, Jang-Seok Choi, Hoon Lee