Abstract: Disclosed herein is an apparatus and method for detecting an emotional change through facial expression analysis. The apparatus for detecting an emotional change through facial expression analysis includes a memory having at least one program recorded thereon, and a processor configured to execute the program, wherein the program includes a camera image acquisition unit configured to acquire a moving image including at least one person, a preprocessing unit configured to extract a face image of a user from the moving image and preprocess the extracted face image, a facial expression analysis unit configured to extract a facial expression vector from the face image of the user and cumulatively store the facial expression vector, and an emotional change analysis unit configured to detect a temporal location of a sudden emotional change by analyzing an emotion signal extracted based on cumulatively stored facial expression vector values.

Abstract: A radio frequency (RF) weak magnetic field detection sensor includes a ferromagnetic core, a pickup coil disposed to surround the ferromagnetic core, a substrate that includes an opening, a core pad connected to the ferromagnetic core and a coil pad connected to the pickup coil, and an insulating tube interposed between the ferromagnetic core and the pickup coil. The insulating tube includes a bobbin around which the pickup coil is wound, and a core hole formed to pass through the bobbin and configured to accommodate the ferromagnetic core.

Abstract: An apparatus and method for transmitting and receiving magnetic field signals in a magnetic field communication system are provided. The apparatus includes a controller configured to generate a communication signal, matching units that are configured to receive the communication signal and that respectively correspond to different matching frequencies, and loop antennas that are connected to the matching units, respectively, and that are configured to convert communication signals according to the different matching frequencies into magnetic transmission signals in the form of magnetic field energy and to transmit the magnetic transmission signals.

Abstract: A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.

Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.

Abstract: A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

Abstract: A method for fabricating a semiconductor includes: forming an etch target layer on a substrate, wherein the etch target layer includes an alternating stack layer and a sacrificial stack layer on the alternating stack layer, and wherein the sacrificial stack layer includes the same material as the alternating stack layer; forming a hard mask pattern on the sacrificial stack layer; etching the etch target layer using the hard mask pattern as an etch barrier to form a plurality of initial high aspect ratio features, the initial high aspect ratio features penetrating through the etch target layer; and removing the hard mask pattern and the sacrificial stack layer to form a plurality of high aspect ratio features.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.

Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.