Abstract: This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

Abstract: This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter.

Abstract: A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter.

Abstract: Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block.

Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter.

Abstract: Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block.

Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter.