Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: A technique to use an auxiliary varactor coupled to a tuning varactor, in which a temperature compensated bias signal adjusts a bias on the auxiliary varactor to maintain a voltage controlled oscillator (VCO) from drifting in frequency as operating temperature for the VCO changes.

Abstract: A technique to use a two-step calibration procedure to calibrate a voltage controlled oscillator (VCO) of a phase-locked loop. The first calibration step is an open-loop calibration procedure in which a control voltage of the VCO is temperature compensated and the VCO is tuned using a search routine to generate a corresponding output frequency based on the control voltage. The second step is a closed-loop calibration procedure to adjust the tuning components of the VCO to correct for a 1 LSB error.

Abstract: A technique to use an auxiliary varactor coupled to a tuning varactor, in which a temperature compensated bias signal adjusts a bias on the auxiliary varactor to maintain a voltage controlled oscillator (VCO) from drifting in frequency as operating temperature for the VCO changes.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A quantizer is described for use in a flash analog to digital converter (ADC), which may be implemented as part of an integrated wireless transceiver or other highly integrated electrical circuit. The quantizer may be configured to operate within such a flash ADC in an accurate manner within a desired voltage range, while minimizing factors that may otherwise lead to errors in the analog-to-digital conversion process. For example, a comparator of the quantizer may be used that has properties that are particularly well-suited for such an environment, where such properties may include, for example, a relatively low input referred offset voltage that is associated with a preamplifier of the comparator.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A quantizer is described for use in a flash analog to digital converter (ADC), which may be implemented as part of an integrated wireless transceiver or other highly integrated electrical circuit. The quantizer may be configured to operate within such a flash ADC in an accurate manner within a desired voltage range, while minimizing factors that may otherwise lead to errors in the analog-to-digital conversion process. For example, a comparator of the quantizer may be used that has properties that are particularly well-suited for such an environment, where such properties may include, for example, a relatively low input referred offset voltage that is associated with a preamplifier of the comparator.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: An apparatus and method are described that provide efficient testing of an integrated circuit wireless transceiver. A digital to analog converter and suitable connection and control logic are integrated on the chip to allow testing of the internal parts of the transceiver by selecting one of a number of predefined test points within the transceiver circuitry. The control logic may configure the digital to analog converter differently, depending on which test point is selected. Also, the digital to analog converter may experience an offset voltage, depending on which test point is selected. Thus, the digital to analog converter may be a current-source digital to analog converter having an offset current source to counter the offset voltage.

Abstract: A transceiver front end includes a transmit/receive (T/R) switch, a first balun, a second balun, a low noise amplifier, a power amplifier, and compensation circuitry. The T/R switch is operably coupled to an antenna for receiving inbound radio frequency (RF) signals and for transmitting outbound RF signals. The first balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The second balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The low noise amplifier is operably coupled the differential winding of the first balun. The power amplifier is operably coupled to the differential winding of the second balun. The compensation circuitry is operably coupled to the first balun to compensate for at least one of phase imbalance, amplitude imbalance, and impedance imbalance of the first balun.

Abstract: Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW) NMOS transistor coupled to an amplifier core. The TW NMOS transistor may track process and temperature variations (PVT) of at least one NMOS transistor within the amplifier core. A drain of the TW NMOS transistor may be coupled to a first inductor and the first inductor may be coupled to a first voltage source. The first voltage source may generate a standard voltage of about 1.2V. A source of the TW NMOS transistor may be coupled to a second inductor and the second inductor may be coupled to the first voltage source. A gate of the TW NMOS transistor may be coupled to a second voltage source, where the second voltage source may generate a standard voltage of about 2.5V.

Abstract: A signal strength indicator circuit including a set of rectifiers. The set of rectifiers include an asymmetric switching pair of rectifiers that may be configured to provide an output signal that is inversely proportional to an input signal obtained from a device in a telecommunications system. The pair may be connected directly on one side thereof to a power supply and may be connected on another side thereof to the power supply through a resistor. Also, a method of processing a signal received by a signal strength indicator circuit.

Abstract: A signal strength indicator circuit that includes a first amplifier configured to receive a first input signal from a first mixer and a second input signal from a second mixer;. The circuit also includes a second amplifier configured to receive a first set of differential inputs from the first amplifier. The circuit further includes a third amplifier configured to receive a second set of differential inputs from the second amplifier stage. Even further, the circuit includes an output port for emitting an output signal that is a rectified combination of the first input signal and the second input signal. Also, a method of processing signals input into a signal strength indicator circuit.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

Abstract: Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW) NMOS transistor coupled to an amplifier core. The TW NMOS transistor may track process and temperature variations (PVT) of at least one NMOS transistor within the amplifier core. A drain of the TW NMOS transistor may be coupled to a first inductor and the first inductor may be coupled to a first voltage source. The first voltage source may generate a standard voltage of about 1.2V. A source of the TW NMOS transistor may be coupled to a second inductor and the second inductor may be coupled to the first voltage source. A gate of the TW NMOS transistor may be coupled to a second voltage source, where the second voltage source may generate a standard voltage of about 2.5V.