Patents by Inventor Janice D. Makos

Janice D. Makos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shallow trench isolation planarization using self aligned isotropic etch
    Patent number: 6686283
    Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan, Janice D. Makos, Arun Sivasothy, Troy A. Yocum, Jaideep Mavoori, Wayne A. Bather, Joe G. Tran, Ju-Ai Ruan, Michelle L. Hartsell, Gregory B. Shinn
  • Process for dielectric stenciled microcircuits
    Patent number: 4336320
    Abstract: The present invention is directed to a process for complex, high density microcircuits in which thick film dielectric pastes are photolithography patterned into high resolution stencils to produce complementary conductor circuitry patterns, the voids of the developed dielectric stencil are filled with thick film conductor paste, and then there is a cofiring of the conductor and the dielectric. With this new process the number of separate firing operations is reduced. The reduction in the number of firings is important in multilevel hybrid structures.
    Type: Grant
    Filed: March 12, 1981
    Date of Patent: June 22, 1982
    Assignee: Honeywell Inc.
    Inventors: John P. Cummings, Janice D. Makos, David E. Pitkanen