Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: A method for design auditing by automating ways of auditing data produced by process steps is disclosed. The invention automates the process of auditing to account for complex methodology conditions. It also automates auditing of values of data produced by methodology steps. The invention provides a means of grouping task and information within a program and of preserving parent-child relationships.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: A method for design auditing by automating ways of auditing data produced by process steps is disclosed. The invention automates the process of auditing to account for complex methodology conditions. It also automates auditing of values of data produced by methodology steps. The invention provides a means of grouping task and information within a program and of preserving parent-child relationships.

Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.