Patents by Inventor Janice Monzet

Janice Monzet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
    Patent number: 8278165
    Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 2, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Rohit Pal, Janice Monzet
  • METHODS FOR PROTECTING FILM LAYERS WHILE REMOVING HARDMASKS DURING FABRICATION OF SEMICONDUCTOR DEVICES
    Publication number: 20110086495
    Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.
    Type: Application
    Filed: October 12, 2009
    Publication date: April 14, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rohit PAL, Janice MONZET