Abstract: This invention provides a multilayer pinned reference layer for a magnetic device. In a particular embodiment a magnetic tunnel junction cell is provided. Each magnetic memory tunnel junction cell provides at least one ferromagnetic data or sense layer, an intermediate layer in contact with the data layer, and a multilayer pinned ferromagnetic reference layer. The multilayer pinned reference layer is in contact with the intermediate layer, opposite from the data layer. The multilayer pinned reference layer is characterized by at least one first layer of ferromagnetic material and at least one second layer of ferromagnetic material in physical contact with the first layer and magnetically coupled to the first layer. The first and second layer self seed to provide a <111> crystal texture used in establishing the pinning magnetic field of the reference layer.

Abstract: A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.

Abstract: An aspect of the present invention is an MRAM device. The MRAM device includes a plurality of magnetic memory elements, a sense line coupled to the plurality of magnetic memory elements for sensing a magnetic orientation of each of the plurality of magnetic memory elements wherein the sense line includes a first via and a second via and wherein the sense line is utilized to thermally assist in switching a magnetic orientation of at least one of the plurality of magnetic memory elements.

Abstract: A thin film device and a method of providing thermal assistance therein is disclosed. Accordingly, a heater material is utilized to thermally assist in the operation of the thin film device. By utilizing a heater material to thermally assist in the operation of the thin film device, a substantial improvement in the accuracy and performance of the thin film device is achieved. A first aspect of the present invention is a thin film device. The thin film device includes at least one patterned thin film layer, a heater material coupled to the at least one patterned thin film layer for providing thermal assistance to the at least one of the patterned thin film layers and a conductor coupled to the heater material for supplying energy to the heater material.

Abstract: A magneto-resistive element is constructed. A ferromagnetic sense layer is deposited on a surface. The ferromagnetic sense layer is patterned. An etch is performed in preparation for depositing a dielectric layer. The dielectric layer is deposited over the sense layer. A ferromagnetic pinned layer is deposited over the dielectric layer.

Abstract: A resistive cross point array memory device comprising a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction such that a plurality of cross points is formed at intersections between the word and bit lines, and at least one memory element formed in at least one of the cross points. The memory element comprises a first tunnel junction having a bottom conductor, a top conductor, a barrier layer adjacent the bottom conductor, and wherein the bottom conductor comprises a non-uniform upper surface.

Abstract: A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.

Abstract: A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The solid-state memory includes circuitry for reducing leakage current among the conductors thereby increasing signal to noise ratio during read operations.

Abstract: A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: The present invention provides a colossal magnetoresistant sensor, and in particular a colossal magnetoresistant sensor capable of responding to the low fields emanating from the recording media. The recording media typically emanates a low field on the order of 20 Oe which is insufficient to result in a significant change in resistance in a CMR layer of material. The colossal magnetoresistant sensor is comprised of a first magnetic layer; a colossal magnetoresistant layer and a second magnetic layer, where the colossal magnetoresistant layer is positioned between the first magnetic layer and a second magnetic layer. The first and second magnetic layers surrounding the colossal magnetoresistant layer control the field through and therefore the resistance of the CMR layer.