Abstract: A high/low and low/high analogue level converter circuit for integrated circuits in which a high/low converter circuit comprises, supplied at a first voltage value, a converter module which receives a logic input signal of analogue level adapted to this first voltage value and delivers a logic signal inverted and replicated with analogue level adapted to this first voltage value, and, supplied at a second voltage value, a differential converter module which from inverted and replicated logic signals delivers a converted logic input signal with analogue level adapted to second voltage value.

Abstract: A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: A three-state output interfacing device for a CMOS memory that comprises a stage for selective control of the device, receiving an input signal (I) at the bit frequency and a control signal (e) and making it possible to deliver, on two ports (A) and (B), either complemented signals (I), or distinct logic levels for driving the device into the high-impedance state, a first inverter stage delivering first inverted logic signals, from the ports (A) and (B), on two ports (C) and (D), a second inverter stage delivering second inverted signals from the ports (C) and (D), a stage for reducing the analog difference between the second inverted signals and for switching the output interfacing device into high-impedance state at ports (E) and (F), and an output stage receiving the signals from the ports (E) and (F) after reduction of analog difference and making it possible to fix and balance the current for charging and discharging the output capacitance of the output interfacing device and its high-impedance switching