Abstract: A controller for a voltage converter, such as a buck converter, includes: a switching regulator circuit having high side and low side switches; comparators configured to compare a voltage of an output circuit to reference voltages; and a control circuit coupled to the current comparators, configured to receive outputs from the comparators, and configured to generate a control signal for alternatingly switching the high side and low side switches off and on, such that the low side switch is off when the high side switch is on, and the high side switch is off when the low side switch is on, and wherein the control circuit includes a latching circuit configured to latch a signal corresponding to at least one of the outputs from the comparators. A method of operating a buck converter in connection with a fixed high-frequency automotive radar system, with reliable over-current detection, is also disclosed.

Abstract: In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.

Abstract: A controller for a voltage converter, such as a buck converter, includes: a switching regulator circuit having high side and low side switches; comparators configured to compare a voltage of an output circuit to reference voltages; and a control circuit coupled to the current comparators, configured to receive outputs from the comparators, and configured to generate a control signal for alternatingly switching the high side and low side switches off and on, such that the low side switch is off when the high side switch is on, and the high side switch is off when the low side switch is on, and wherein the control circuit includes a latching circuit configured to latch a signal corresponding to at least one of the outputs from the comparators. A method of operating a buck converter in connection with a fixed high-frequency automotive radar system, with reliable over-current detection, is also disclosed.

Abstract: In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.

Abstract: A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.

Abstract: A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.

Abstract: To improve power converter ON-time generation, an example apparatus includes: a phase frequency detector to determine a phase difference between a first signal and a second signal; a first pulse generator to generate a first time signal at a second time, in which the first signal is associated with a first time delay based on the phase difference; and a second pulse generator coupled to the first pulse generator. The second pulse generator is configured to: generate a second time signal at a third time, in which the third time is after the second time; and obtain a digital word based on the phase difference at a first time, in which the first time is before the second time and the third time, and the second time signal is associated with a second time delay based on the phase difference.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.

Abstract: In some examples, an apparatus comprises a switching regulator circuit, an output circuit, a duty cycle comparison circuit, a current comparison circuit, and a switching regulator control circuit. The switching regulator circuit switches between first and second voltages. The output circuit has a voltage input and a voltage output and generates a signal based on the first and second voltages. The duty cycle comparison circuit asserts a first signal responsive to a voltage at the voltage output exceeding a product of a multiplier and a reference signal. The current comparison circuit asserts a second signal responsive to a voltage at the voltage input exceeding a first reference voltage and to assert a third signal responsive to the voltage at the voltage input being below a second reference voltage. The switching regulator control circuit controls the switching regulator circuit based on the first, the second, and the third signals.

Abstract: In some examples, an apparatus comprises a switching regulator circuit, an output circuit, a duty cycle comparison circuit, a current comparison circuit, and a switching regulator control circuit. The switching regulator circuit switches between first and second voltages. The output circuit has a voltage input and a voltage output and generates a signal based on the first and second voltages. The duty cycle comparison circuit asserts a first signal responsive to a voltage at the voltage output exceeding a product of a multiplier and a reference signal. The current comparison circuit asserts a second signal responsive to a voltage at the voltage input exceeding a first reference voltage and to assert a third signal responsive to the voltage at the voltage input being below a second reference voltage. The switching regulator control circuit controls the switching regulator circuit based on the first, the second, and the third signals.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in power converters, the apparatus comprising: a first single shot circuit to, during runtime of a power converter, generate a clock signal based on an adaptive delay, the adaptive delay based on a count value of a counter; a pulse comparator coupled to an adaptation pulse generator, the pulse comparator to, during runtime of the power converter: compare a first duration of the adaptation pulse to a second duration of a reference pulse; and adjust the count value of the counter; and a ready detector coupled to the pulse comparator, the ready detector to, in response to a trigger event, transmit, during runtime of the power converter, the count value to a second single shot circuit.

Abstract: A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.

Abstract: An apparatus includes a phase frequency detector having a detector output and first and second inputs, the phase frequency detector configured to provide a phase difference signal at the detector output responsive to the first and second inputs. The apparatus also includes a gain controller having a controller input and a controller output, the controller input coupled to the detector output, and the gain controller configured to provide a digital value at the controller output responsive to the phase difference signal and a duty cycle. The apparatus also includes a pulse generator having a generator output and first and second generator inputs, the first generator input coupled to the controller output, the second generator input coupled to the second detector input, the pulse generator configured to provide a generator signal at the generator output responsive to the digital value and the second generator input.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.

Abstract: A system includes a digital phase-locked loop (DPLL) having a loop filter and a digitally-controlled oscillator (DCO). The system also includes a clock generator coupled to an output of the DPLL, and a plurality of clock domains coupled to the clock generator. The DPLL is configured to transition between a low power mode and a normal mode, wherein the loop filter is configured to maintain its value when the DPLL transitions from the normal mode to the low power mode. The DCO is configured to output a DCO clock signal based on the maintained loop filter value when the DPLL transitions from the low power mode to the normal mode.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to bypass sensed signals in power converters. The disclosed methods, apparatus, systems and articles of manufacture provide an apparatus to bypass sensed signals in power converters, the apparatus comprising: a first single shot circuit to, during runtime of a power converter, generate a clock signal based on an adaptive delay, the adaptive delay based on a count value of a counter; a pulse comparator coupled to an adaptation pulse generator, the pulse comparator to, during runtime of the power converter: compare a first duration of the adaptation pulse to a second duration of a reference pulse; and adjust the count value of the counter; and a ready detector coupled to the pulse comparator, the ready detector to, in response to a trigger event, transmit, during runtime of the power converter, the count value to a second single shot circuit.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve power converter ON-time generation. An example apparatus includes a phase frequency detector to determine a phase difference between a first signal and a second signal, a first pulse generator to generate a first time signal at a second time, the first time signal associated with a first time delay based on the phase difference, and a second pulse generator coupled to the first pulse generator to generate a second time signal at a third time, the third time after the second time, the second pulse generator to obtain a digital word based on the phase difference at a first time, the first time before the second time and the third time, the second time signal associated with a second time delay based on the phase difference.

Abstract: Methods and apparatus to digitally control pulse frequency modulation pulses in power converters are disclosed. An example apparatus includes a low-side controller structured to, when an inductor current corresponds to a first current direction during a low-side control signal of a power converter, decrease a first duration of the low-side control after the first duration; and when the inductor current corresponds to a second current direction during the low-side control signal of the power converter, increase the first duration of the low-side control after the first duration; and a high-side controller structured to, when a sum of the first duration and a second duration corresponding to a high-side control of the power converter does not satisfy target pulse length, increase a third duration of the high-side control after the third duration; and when the sum of the first duration and the second duration satisfies the target pulse length, decrease the third duration of the subsequent high-side control.