Abstract: There is provided a system and method of a method of detecting a local shape deviation of a structural element in a semiconductor specimen, comprising: obtaining an image comprising an image representation of the structural element; extracting, from the image, an actual contour of the image representation; estimating a reference contour of the image representation indicative of a standard shape of the structural element, wherein the reference contour is estimated based on a Fourier descriptor representative of the reference contour, the Fourier descriptor being estimated using an optimization method based on a loss function specifically selected to be insensitive to local shape deviation of the actual contour; and performing one or more measurements representative of one or more differences between the actual contour and the reference contour, the measurements indicative of whether a local shape deviation is present in the structural element.

Abstract: There is provided a system and method of a method of detecting a local shape deviation of a structural element in a semiconductor specimen, comprising: obtaining an image comprising an image representation of the structural element; extracting, from the image, an actual contour of the image representation; estimating a reference contour of the image representation indicative of a standard shape of the structural element, wherein the reference contour is estimated based on a Fourier descriptor representative of the reference contour, the Fourier descriptor being estimated using an optimization method based on a loss function specifically selected to be insensitive to local shape deviation of the actual contour; and performing one or more measurements representative of one or more differences between the actual contour and the reference contour, the measurements indicative of whether a local shape deviation is present in the structural element.

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.

Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.