Abstract: Described herein are systems and methods for a media controller configured to associate data from a media device received using a media device interface with actions on the media devices. The associated data and actions may be used to build a media device interface command map. The media device interface command map may be used by the media controller to control the media device. A user interface provided by the media controller may thus be used to control disparate devices, allowing for a coordinated and consistent user experience across multiple media devices, even when they are from different manufacturers.

Abstract: Described herein are systems and methods of processing images comprising border features including, but not limited to letterboxing, pillarboxing, or windowboxing. Between the border features is primary content. The processing comprises scaling the primary content to increase prominence during presentation. Space unused during the presentation is filled with a revised border. Supplemental content may be presented in at least a portion of the revised border.

Abstract: Described herein are systems and methods for a media controller configured to associate data from a media device received using a media device interface with actions on the media devices. The associated data and actions may be used to build a media device interface command map. The media device interface command map may be used by the media controller to control the media device. A user interface provided by the media controller may thus be used to control disparate devices, allowing for a coordinated and consistent user experience across multiple media devices, even when they are from different manufacturers.

Abstract: The color patterned front light (CPFL) may be implemented by shining light through a side of a CPFL panel that is situated adjacent to and in front of a monochromic reflective display (MRD). The CPFL may direct one of red, green, blue, or white light through a rear surface of the panel and onto each of the pixels in the MRD. The pixels may be grouped in blocks, such as n-by-m or n-by-n blocks of pixels. The pixels in the block may be selectively activated by the MRD to either absorb the light or reflect the light shone on the respective pixel. By adjusting the representation of the pixels in the MRD, the block may appear to change color based on the colored light from the CPFL that is reflected outward from the display.

Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

Abstract: A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

Abstract: A clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The divider circuit has a clock input, a divider reset input, and a divided clock output. The synchronizer has a clock input, and a synchronous reset input, and a synchronized reset output having an active edge aligned with an active edge of the clock. The synchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider.

Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

Abstract: A data bus arbitration system is disclosed including a bus status monitor which is coupled to a data bus and generates a bus status signal for use by an arbiter. The arbiter is coupled to a number of requesters, each of which belongs to a distinct class of requesters. The arbiter arbitrates between multiple requests using heuristics dependent upon the classes of the requesters. The nature of one class of requestors is that the requestors have real time requirements which must be met in order to maintain data integrity within the system. The nature of a second class of requestors is such that the requestors have semi-real time requirements which must be met in order to maintain data integrity within the system. The nature of the system is such that the available bandwidth must be utilized very efficiently in order to maintain data integrity within the system.

Abstract: Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.

Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

Abstract: Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.

Abstract: Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.