Patents by Inventor Janos Veres
Janos Veres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200156387Abstract: Disclosed are a substrate package, a method of fabricating the substrate package, and a system including the substrate package. The substrate package includes a stack of substrate sheets in an individual form, a continuous form, or a roll form. The stack has a sidewall defined by edges of the substrate sheets and a mark on the sidewall includes mark segments on respective edges. The mark segments vary such that one or more of the mark segments have a respective segment characteristic, such as a length. The segment characteristic can encode information about an attribute of the substrate sheet, such as a physical characteristic of the sheet.Type: ApplicationFiled: January 23, 2020Publication date: May 21, 2020Inventors: Janos Veres, Antonio St. Clair Lloyd Williams, Marc E. Mosko
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Patent number: 10628725Abstract: Systems and methods for operating a tag system. The methods comprise performing the following operations by a tag having an antenna: emitting a signal at a first frequency spectrum, if the tag is not proximate to a tag modulation marker; and emitting a signal at a second frequency spectrum, if the tag is proximate to the tag modulation marker.Type: GrantFiled: January 17, 2019Date of Patent: April 21, 2020Assignee: Palo Alto Research Center IncorporatedInventors: Ping Mei, Janos Veres
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Publication number: 20200101764Abstract: Disclosed are a substrate package, a method of fabricating the substrate package, and a system including the substrate package. The substrate package includes a stack of substrate sheets in an individual form, a continuous form, or a roll form. The stack has a sidewall defined by edges of the substrate sheets and a mark on the sidewall includes mark segments on respective edges. The mark segments vary such that one or more of the mark segments have a respective segment characteristic, such as a length. The segment characteristic can encode information about an attribute of the substrate sheet, such as a physical characteristic of the sheet.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Janos Veres, Antonio St. Clair Lloyd Williams, Marc E. Mosko
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Patent number: 10596830Abstract: Disclosed are a substrate package, a method of fabricating the substrate package, and a system including the substrate package. The substrate package includes a stack of substrate sheets in an individual form, a continuous form, or a roll form. The stack has a sidewall defined by edges of the substrate sheets and a mark on the sidewall includes mark segments on respective edges. The mark segments vary such that one or more of the mark segments have a respective segment characteristic, such as a length. The segment characteristic can encode information about an attribute of the substrate sheet, such as a physical characteristic of the sheet.Type: GrantFiled: September 28, 2018Date of Patent: March 24, 2020Assignee: Palo Alto Research Center IncorporatedInventors: Janos Veres, Antonio St. Clair Lloyd Williams, Marc E. Mosko
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Publication number: 20190124757Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: ApplicationFiled: November 14, 2018Publication date: April 25, 2019Applicant: Palo Alto Research Center IncorporatedInventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Patent number: 10186776Abstract: A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.Type: GrantFiled: June 11, 2018Date of Patent: January 22, 2019Assignee: Palo Alto Research Center IncorporatedInventors: David K. Biegelsen, JengPing Lu, Janos Veres
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Patent number: 10165677Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: GrantFiled: December 10, 2015Date of Patent: December 25, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Publication number: 20180309200Abstract: A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.Type: ApplicationFiled: June 11, 2018Publication date: October 25, 2018Inventors: David K. Biegelsen, JengPing Lu, Janos Veres
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Patent number: 10020457Abstract: A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.Type: GrantFiled: July 18, 2017Date of Patent: July 10, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, David Eric Schwartz, Janos Veres
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Patent number: 9997837Abstract: A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.Type: GrantFiled: April 19, 2017Date of Patent: June 12, 2018Assignee: Palo Alto Research Center IncorporatedInventors: David K. Biegelsen, JengPing Lu, Janos Veres
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Patent number: 9952082Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.Type: GrantFiled: May 10, 2016Date of Patent: April 24, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
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Patent number: 9874984Abstract: Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.Type: GrantFiled: September 30, 2015Date of Patent: January 23, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Ping Mei, Tse Nga Ng, Janos Veres
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Patent number: 9857031Abstract: A light emitting diode (LED) lighting device includes at least one LED assembly comprising a substrate and two or more LEDs configured to generate light spaced apart along the substrate. A cured structural coating is disposed on at least a portion of the LED assembly, wherein the cured structural coating is configured to maintain the LED assembly in a predetermined shape. The substrate of the LED assembly may comprise an elongated and/or flexible substrate.Type: GrantFiled: December 12, 2016Date of Patent: January 2, 2018Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Janos Veres, Philipp Schmaelzle, Christopher Paulson, Ashish Pattekar, Patrick Y. Maeda
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Publication number: 20170328761Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.Type: ApplicationFiled: May 10, 2016Publication date: November 16, 2017Applicant: Palo Alto Research Center IncorporatedInventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
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Publication number: 20170317303Abstract: A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.Type: ApplicationFiled: July 18, 2017Publication date: November 2, 2017Inventors: TSE NGA NG, DAVID ERIC SCHWARTZ, JANOS VERES
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Patent number: 9735382Abstract: Multiple thin film transistors are aligned in serial and parallel orientation. A second source region is disposed between a first source region and a first drain region. A second drain region is disposed between the first source region and the first drain region. The second drain region and the second source region substantially coincide. A first gate is disposed between the first source region and the coinciding second source and second drain regions. A second gate region is disposed between the first drain region and the coinciding second source and second drain regions. An semiconductor is disposed between the first source region, the first drain region, and the coinciding second source and second drain regions. A dielectric material is disposed between the semiconductor substrate and the first and second gates.Type: GrantFiled: November 8, 2012Date of Patent: August 15, 2017Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, David Eric Schwartz, Janos Veres
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Publication number: 20170171958Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.Type: ApplicationFiled: December 10, 2015Publication date: June 15, 2017Applicant: Palo Alto Research Center IncorporatedInventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
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Patent number: 9639050Abstract: A method is disclosed in the context of a system comprises an electrophotographic subsystem, a transfer subsystem, an imaging member, and an inking subsystem. The electrophotographic subsystem comprises a photoreceptor, a charging subsystem, an exposure subsystem, and a development subsystem. In operation, the photoreceptor is charged areawise. An exposure pattern is formed by the exposure subsystem on the surface of the charged photoreceptor to thereby write a latent charge image onto the photoreceptor surface. The image is developed with an image definition material, such as a dampening fluid. The image definition material forms a positive pattern of the image to be printed. The image pattern is then transferred to the reimageable surface. The transferred pattern is then developed by selectively applying an ink over regions of image definition material. The inked image may be transferred to a substrate.Type: GrantFiled: July 12, 2012Date of Patent: May 2, 2017Assignees: Xerox Corporation, Palo Alto Research Center IncorporatedInventors: Janos Veres, David K. Biegelsen, Chu-Heng Liu
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Publication number: 20170089519Abstract: A light emitting diode (LED) lighting device includes at least one LED assembly comprising a substrate and two or more LEDs configured to generate light spaced apart along the substrate. A cured structural coating is disposed on at least a portion of the LED assembly, wherein the cured structural coating is configured to maintain the LED assembly in a predetermined shape. The substrate of the LED assembly may comprise an elongated and/or flexible substrate.Type: ApplicationFiled: December 12, 2016Publication date: March 30, 2017Inventors: Janos Veres, Philipp Schmaelzle, Christopher Paulson, Ashish Pattekar, Patrick Y. Maeda
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Publication number: 20170090613Abstract: Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Applicant: Palo Alto Research Center IncorporatedInventors: Ping Mei, Tse Nga Ng, Janos Veres