Abstract: Improved devices and methods for performing Fast Fourier Transforms.

Abstract: User input values define an inspection window for evaluating a desired traffic element portions of a bitstream. Offset and reference values determine the start of the window with respect to the bitstream and values for a filter register and mask registers define the size of the window. As the bitstream ‘passes through’ the window, the bits in the window are compared to bits in the filter and mask registers. Traffic element portions that match the criteria of the window are stored into a storage device formed with a FPGA. Filter controls that are also formed with, the FPGA determine that the window criteria are met; and send a control signal to a capture apparatus gate to permit the current bitstream portion into a storage device that is also formed with the FPGA. The stored element portions are later evaluated by the CMTS and/or operation personnel.

Abstract: In a cable data system that includes a cable modem termination system or CMTS, high-reliability is accomplished by reducing the time required to switch over traffic from a failed circuit to a back up circuit. Fault recovery time to switch over to a spare circuit is reduced by copying the operational parameters used in each of the active circuits into a spare circuit such that upon the failure of an active circuit, the spare circuit needs only to be instructed which set of operational parameters for a particular failed circuit to use. Clock counters that are continuously incremented in active circuits can be copied into a newly installed circuit by copying into a local register for the newly installed circuit, a future value of a clock counter.