Patents by Inventor Janusz P. Jurski

Janusz P. Jurski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817454
    Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
  • Patent number: 10649832
    Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Kasper Wszolek, Janusz P. Jurski, Piotr Kwidzinski, Robert C. Swanson, Madhusudhan Rangarajan
  • Patent number: 10612980
    Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
  • Publication number: 20190251055
    Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Applicant: Intel Corporation
    Inventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
  • Publication number: 20190057000
    Abstract: Embodiments of the claimed invention include a computing device having a host processor for executing a firmware environment and a manageability controller. The firmware environment reserves a frame buffer in main memory and loads a graphics protocol driver to provide the frame buffer to an operating system of the computing device. The operating system renders graphical images to the frame buffer using a graphics driver. The manageability controller reads the graphical image from the frame buffer and may transmit the graphical image to a remote computing device. In response to a fatal error of the computing device, the manageability controller may store the graphical image to a non-volatile storage device. The host processor may assert a host reset signal in response to the fatal error, and the manageability controller may send an acknowledgment to the host processor after storing the graphical image. Other embodiments are described and claimed.
    Type: Application
    Filed: August 15, 2017
    Publication date: February 21, 2019
    Inventors: Kasper Wszolek, Janusz P. Jurski, Piotr Kwidzinski, Robert C. Swanson, Madhusudhan Rangarajan
  • Publication number: 20180372551
    Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.
    Type: Application
    Filed: June 21, 2017
    Publication date: December 27, 2018
    Inventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan