Abstract: A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.

Abstract: A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.

Abstract: An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.

Abstract: A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.

Abstract: A method of fabricating a passive device on a printed circuit board. A first substrate and a second substrate are provided. Each of the first and the second substrates has an insulation core layer and a conductive layer on the insulation core layer. A dielectric layer is coated on the first substrate to cover a surface of the conductive layer thereon as an internal dielectric layer. The second substrate is laminated onto the internal dielectric layer, so that the conductive layers of the first and the second substrates are adjacent to the internal dielectric layer.

Abstract: A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.

Abstract: A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.

Abstract: A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating.

Abstract: A method of producing an external connector is provided. A substrate is provided and a plurality of pads are formed on the substrate. A copper layer is formed on the substrate to cover the pads. A patterned photoresist is formed on the copper layer. The patterned photoresist has a plurality of openings to expose the copper layer which corresponds to the pads. Then, a conductive plug is formed on the exposed copper layer. The patterned photoresist is removed, and the copper layer which is not covered by the conductive plug is subsequently removed. A solder resist is formed over the substrate to cover the pads and the conductive plug. A portion of the solder resist is removed until the conductive plug is exposed, wherein the solder resist is as high as the conductive plug.

Abstract: A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.

Abstract: A method for burn-in testing a complete wafer comprising the steps of first providing a wafer, and then forming a plurality of bumps thereon. Next, a tape-automated bonding tape having a plurality of bonding pads is designed and fabricated, wherein each bonding pad includes a corresponding circuit and an external contact point. Then, electrical connections between the bonding pads and the bumps are made and a plurality of voltages and currents are supplied through the tape-automated bonding tape for carrying out burn-in tests. Bum-in tests are performed for the whole wafer. Defective chips are singled out after the wafer is cut up and only good chips are used for subsequent packaging. Therefore, production cost can be saved and packaging yield can be increased. Furthermore, a multiple circuit layers design can be employed to fabricate the tape-automated bonding tape. Consequently, circuits necessary for carrying out the burn-in test for the whole wafer is simplified.