Abstract: A method and apparatus is used to reduce the unnecessary calculation of the video images motion estimation by identifying the all-zero block or zero-motion vector macroblock in advance. The method of computation reduction stops the motion estimation searching, referring to the condition of the absolute difference and the quantization parameter, and stops the following computation of the Discrete Cosine Transform and quantization. The reference critical value is set according to the motionless residue value of previous frame or the constant critical value to determine the zero-motion vector macroblock in the images.

Abstract: An apparatus with new fixed-coefficient recursive structures for computing discrete cosine transforms with the power-of-two length is disclosed. The fixed-coefficient recursive structures are developed from exploration of periodicity embedded in transform bases, whose indices can form a complete residue system or a complete odd residue system. Distinctively, we found that properly selected fixed-coefficient filters achieve lower round-off errors than the nominal variable-coefficient ones for computing DCTs in finite-word-length machines.

Abstract: A processor is provided for transforming N.times.N discrete cosine transform (DCT) coefficients F.sub.uv inputted from a run-length-code 5 (RLC) decoder and arranged in an input order into an image data f.sub.jk in an integrated circuit through a 2-D inverse discrete cosine transform (IDCT) procedure wherein subscripts u and v of DCT coefficients F.sub.uv are input frequency indices respectively having least significant bits (LSB) u.sub.0 and v.sub.0 having an exclusive-OR (XOR) and subscripts j and k of image data f.sub.jk are spatial indices generated by the integrated circuit, which comprises a cosine pre-multiplier array for computing cosine-weighted DCT coefficients, a principal subkernel mapper utilizing the cosine-weighted DCT coefficients by first referring to the indices u and v for forming a principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv, an N.times.N accumulating matrix operating with the principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.

Abstract: In this invention, we introduce a connection indexing algorithm for realizing the arithmetic coding in finite wordlength processors. By determining the number of encoded information bits according to a difference between the finite wordlength and a residual termination parameter defined by the maximum difference of the information bits of any two adjacent symbols in the ordered-probabilities symbols set, the information of the last symbol is split into the current and the subsequent finite length codewords. The two or three encoded symbols split into the current and the subsequent finite length codewords are decoded independently, and the indices thereof are added to form a decoded symbol having an index equal to a sum of the addition.

Abstract: A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.