Patents by Inventor Jared L. Zerbe

Jared L. Zerbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220140833
    Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
    Type: Application
    Filed: November 17, 2021
    Publication date: May 5, 2022
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Sanjay Pant
  • Publication number: 20220130445
    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
    Type: Application
    Filed: November 8, 2021
    Publication date: April 28, 2022
    Inventors: Jared L. ZERBE, Frederick A. WARE
  • Publication number: 20220103405
    Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
    Type: Application
    Filed: October 15, 2021
    Publication date: March 31, 2022
    Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian S. Leibowitz, Vladimir Stojanovic
  • Patent number: 11290305
    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: March 29, 2022
    Assignee: Highlands, LLC
    Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen
  • Publication number: 20220070032
    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
    Type: Application
    Filed: August 12, 2021
    Publication date: March 3, 2022
    Inventors: Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin
  • Patent number: 11258577
    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 22, 2022
    Assignee: Rambus Inc.
    Inventor: Jared L. Zerbe
  • Patent number: 11210583
    Abstract: Systems and methods are disclosed for a server generating a plurality of proxy prediction models for each of a plurality of applications for use by client devices. Providing a prediction model based on a data distribution that more closely matches the user private data of the actual user of the client device, as opposed to a generic model, can improve the accuracy of predictions and improve the benefits to the user of the client device. The plurality of prediction models are generated by a server and provided to a plurality of clients. For a particular application, a client device can use previously collected private user data to select one of the plurality of prediction models for the application as being a closest matching prediction model to use for a particular user.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: December 28, 2021
    Assignee: APPLE INC.
    Inventors: Binu K. Mathew, Julia C. Ng, Jared L. Zerbe
  • Publication number: 20210398980
    Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 23, 2021
    Inventors: Jared L. Zerbe, Emerson S. Fang, Jun Zhai, Shawn Searles
  • Patent number: 11195570
    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 7, 2021
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Frederick A. Ware
  • Patent number: 11184012
    Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 23, 2021
    Assignee: Apple Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Sanjay Pant
  • Patent number: 11181941
    Abstract: The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 23, 2021
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Jared L. Zerbe
  • Patent number: 11165613
    Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 2, 2021
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian S. Leibowitz, Vladimir Stojanovic
  • Patent number: 11115247
    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin
  • Patent number: 11063046
    Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Apple Inc.
    Inventors: Jared L. Zerbe, Emerson S. Fang, Jun Zhai, Shawn Searles
  • Patent number: 11063791
    Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Rambus Inc.
    Inventors: Qi Lin, Brian Leibowitz, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe
  • Patent number: 10951218
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 16, 2021
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Publication number: 20210075651
    Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.
    Type: Application
    Filed: August 21, 2020
    Publication date: March 11, 2021
    Inventors: Vladimir M. Stojanovic, Andrew C. Ho, Anthony Bessios, Bruno W. Garlepp, Grace Tsang, Mark A. Horowitz, Jared L. Zerbe, Jason C. Wei
  • Publication number: 20210067384
    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 4, 2021
    Inventors: Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen
  • Publication number: 20210064116
    Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 4, 2021
    Applicant: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
  • Publication number: 20210049118
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 18, 2021
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble