Patents by Inventor Jared Stark

Jared Stark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BRANCH PREFETCH MECHANISMS FOR MITIGATING FRONTEND BRANCH RESTEERS
    Publication number: 20220100520
    Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 26, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Gilles Pokam, Jared Stark, Niranjan Kumar Soundararajan, Oleg Ladin
  • USING COMPUTATION HISTORIES TO MAKE PREDICTIONS
    Publication number: 20070088936
    Abstract: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 19, 2007
    Applicant: Intel Corporation
    Inventors: Chris Wilkerson, Jared Stark, Renju Thomas
  • Prophet/critic hybrid predictor
    Publication number: 20060036837
    Abstract: A hybrid prophet/critic predictor includes a first branch predictor to provide a first branch prediction for a branch under prediction (BUP) based on a branch history of the BUP and/or a program counter, and also includes a second branch predictor to provide a second branch prediction for the BUP based on a branch future of the BUP.
    Type: Application
    Filed: August 13, 2004
    Publication date: February 16, 2006
    Inventors: Jared Stark, Ayose Falcon-Samper
  • Non-vital loads
    Patent number: 6668306
    Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Ryan N. Rakvic, John P. Shen, Bohuslav Rychlik, Christopher B. Wilkerson, Jared Stark, Hong Wang
  • Non-vital loads
    Publication number: 20020188804
    Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 12, 2002
    Inventors: Ryan N. Rakvic, John P. Shen, Bohuslav Rychlik, Christopher B. Wilkerson, Jared Stark, Hong Wang