Patents by Inventor Jared W Havican

Jared W Havican has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11874787
    Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Amit K Srivastava, Majid Shushtarian, Anand K Enamandram, Jared W Havican, Jeffrey A Pihlman, Michael J Karas, Ramamurthy Krithivas, Christine Watnik
  • Patent number: 11126245
    Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Justin Madigan, Shaun M. Conrad, Christopher J. Lake, Madhu Thangaraj, Dhinesh Sasidaran, Jared W. Havican
  • Publication number: 20200401205
    Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Justin Madigan, Shaun M. Conrad, Christopher J. Lake, Madhu Thangaraj, Dhinesh Sasidaran, Jared W. Havican
  • Publication number: 20200183872
    Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Amit K Srivastava, Majid Shushtarian, Anand K Enamandram, Jared W Havican, Jeffrey A Pihlman, Michael J Karas, Ramamurthy Krithivas, Christine Watnik