Abstract: The invention relates to a method and arrangement for enhancing a search through a trellis in a detector (220) that is arranged at each stage of the trellis to select a certain set of state indexes of the stage for continuation. The detector (220) is arranged, when each stage of the trellis is calculated, to define more than one unequal threshold value for the values of the state indexes, each threshold value defining one state index group, to calculate for each state index a path metric, to arrange the calculated state indexes into different groups by comparing the path metric value of the state index with the threshold values. Further the detector selects from the groups a certain number of state indexes for continuation in such a manner that starting from the group comprising the highest state indexes, entire groups are selected for continuation until the next entire group does not fit in. From this group only randomly selected state indexes are selected until a given number is collected.

Abstract: A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorted by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. An equalizer in accordance with this invention includes a logical arrangement of a plurality of instantiations of locally coupled processing elements forming a systolic array for processing in common received signal samples having distortion induced by passage through a communication channel. The equalizer outputs soft values for input to a decoder, the soft values representing an approximation of maximum a posteriori (MAP) probabilities. A trellis search procedure is employed to reconstruct estimates of a received signal sequence based on a reduced number of states. The reduced number of states is represented by a plurality of groups determined by partitioning a symbol constellation such that there are fewer groups than possible symbols.

Abstract: A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of operation, to first data sources representing outputs of the multiplier front end. In the first mode of operation the ALUs add together partial products received from the multiplier front end to arrive at a multiplication result. In a second mode of operation the inputs of the plurality of ALUs are switchably or programmably coupled to second data sources for performing at least one of arithmetic and logical operations on data received from the second data sources.

Abstract: The invention relates to a method and arrangement for enhancing a search through a trellis in a detector (220) that is arranged at each stage of the trellis to select a certain set of state indexes of the stage for continuation. The detector (220) is arranged, when each stage of the trellis is calculated, to define more than one unequal threshold value for the values of the state indexes, each threshold value defining one state index group, to calculate for each state index a path metric, to arrange the calculated state indexes into different groups by comparing the path metric value of the state index with the threshold values. Further the detector selects from the groups a certain number of state indexes for continuation in such a manner that starting from the group comprising the highest state indexes, entire groups are selected for continuation until the next entire group does not fit in. From this group only randomly selected state indexes are selected until a given number is collected.

Abstract: The invention relates to an arrangement and method for enhancing a search through a trellis in connection with decoding or channel correction, for instance. When searching through the trellis, the state indexes being processed are divided into more than one subset at each stage of the trellis, the path metrics of the state indexes are defined in the subsets, and a predefined number of state indexes are selected for continuation from each subset on the basis of the metrics.

Abstract: A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorded by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. An equalizer (10) in accordance with this invention includes a logical arrangement of a plurality of instantiations of locally coupled processing elements (12) forming a systolic array for processing in common received signal samples having distortion induced by passage through a communication channel. The equalizer outputs soft values for input to a decoder, the soft values representing an approximation of maximum a posteriori (MAP) probabilities. A trellis search procedure is employed to reconstruct estimates of a received signal sequence based on a reduced number of states. The reduced numbe of states is represented by a plurality of groups determined by partioning a symbol constellation such that there are fewer groups than possible symbols.

Abstract: A method for adapting a bus to data traffic in a system comprising several functional units (311, 312, . . . , 31n) and a bus structure. The functional units are divided into at least two sets so that units, which mainly transfer data with each other belong to a same set and are interfaced with the same separate sub-bus (321; 322). The sub-buses can be united by switches (SW) into a more extensive bus, which is only used when data must be transferred between different sets. Supply voltage of each sub-bus is adjustable and is set the lower the less traffic there is on the bus. The parallel transfer operation makes it possible to increase the transfer capacity of the bus structure without increasing it's clock frequency. Furthermore energy consumption can be reduced by dropping the supply voltage of the bus circuits so that the bus retains the transfer capacity needed.

Abstract: The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched for the inverse value of the square root of a desired number. If the value is found in the look-up table, it is retrieved. If the value is not found in the look-up table, the number is scaled such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation.

Abstract: The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched for the inverse value of the square root of a desired number. If the value is found in the look-up table, it is retrieved. If the value is not found in the look-up table, the number is scaled such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation.

Abstract: A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of operation, to first data sources representing outputs of the multiplier front end. In the first mode of operation the ALUs add together partial products received from the multiplier front end to arrive at a multiplication result. In a second mode of operation the inputs of the plurality of ALUs are switchably or programmably coupled to second data sources for performing at least one of arithmetic and logical operations on data received from the second data sources. In this case the plurality of ALUs can operate together in parallel. In general, the partial products have a width of n-bits, and a width of the ALUs is one of n-bits or less than n-bits.