Patents by Inventor Jari Parviainen

Jari Parviainen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7159167
    Abstract: The invention relates to a method and arrangement for enhancing a search through a trellis in a detector (220) that is arranged at each stage of the trellis to select a certain set of state indexes of the stage for continuation. The detector (220) is arranged, when each stage of the trellis is calculated, to define more than one unequal threshold value for the values of the state indexes, each threshold value defining one state index group, to calculate for each state index a path metric, to arrange the calculated state indexes into different groups by comparing the path metric value of the state index with the threshold values. Further the detector selects from the groups a certain number of state indexes for continuation in such a manner that starting from the group comprising the highest state indexes, entire groups are selected for continuation until the next entire group does not fit in. From this group only randomly selected state indexes are selected until a given number is collected.
    Type: Grant
    Filed: May 26, 2003
    Date of Patent: January 2, 2007
    Assignee: Nokia Corporation
    Inventors: Jari Parviainen, Teemu Sipila
  • Patent number: 7003055
    Abstract: A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorted by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. An equalizer in accordance with this invention includes a logical arrangement of a plurality of instantiations of locally coupled processing elements forming a systolic array for processing in common received signal samples having distortion induced by passage through a communication channel. The equalizer outputs soft values for input to a decoder, the soft values representing an approximation of maximum a posteriori (MAP) probabilities. A trellis search procedure is employed to reconstruct estimates of a received signal sequence based on a reduced number of states. The reduced number of states is represented by a plurality of groups determined by partitioning a symbol constellation such that there are fewer groups than possible symbols.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 21, 2006
    Assignee: Nokia Corporation
    Inventors: Thomas A. Sexton, Jari Parviainen
  • Publication number: 20050177782
    Abstract: The invention relates to a method and arrangement for enhancing a search through a trellis in a detector (220) that is arranged at each stage of the trellis to select a certain set of state indexes of the stage for continuation. The detector (220) is arranged, when each stage of the trellis is calculated, to define more than one unequal threshold value for the values of the state indexes, each threshold value defining one state index group, to calculate for each state index a path metric, to arrange the calculated state indexes into different groups by comparing the path metric value of the state index with the threshold values. Further the detector selects from the groups a certain number of state indexes for continuation in such a manner that starting from the group comprising the highest state indexes, entire groups are selected for continuation until the next entire group does not fit in. From this group only randomly selected state indexes are selected until a given number is collected.
    Type: Application
    Filed: May 26, 2003
    Publication date: August 11, 2005
    Inventors: Jari Parviainen, Teemu Sipila
  • Publication number: 20050086577
    Abstract: The invention relates to an arrangement and method for enhancing a search through a trellis in connection with decoding or channel correction, for instance. When searching through the trellis, the state indexes being processed are divided into more than one subset at each stage of the trellis, the path metrics of the state indexes are defined in the subsets, and a predefined number of state indexes are selected for continuation from each subset on the basis of the metrics.
    Type: Application
    Filed: November 27, 2002
    Publication date: April 21, 2005
    Inventors: Teemu Sipilä, Jari Parviainen
  • Publication number: 20040240591
    Abstract: A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorded by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. An equalizer (10) in accordance with this invention includes a logical arrangement of a plurality of instantiations of locally coupled processing elements (12) forming a systolic array for processing in common received signal samples having distortion induced by passage through a communication channel. The equalizer outputs soft values for input to a decoder, the soft values representing an approximation of maximum a posteriori (MAP) probabilities. A trellis search procedure is employed to reconstruct estimates of a received signal sequence based on a reduced number of states. The reduced numbe of states is represented by a plurality of groups determined by partioning a symbol constellation such that there are fewer groups than possible symbols.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Inventors: Thomas A. Sexton, Jari Parviainen
  • Publication number: 20040153592
    Abstract: A method for adapting a bus to data traffic in a system comprising several functional units (311, 312, . . . , 31n) and a bus structure. The functional units are divided into at least two sets so that units, which mainly transfer data with each other belong to a same set and are interfaced with the same separate sub-bus (321; 322). The sub-buses can be united by switches (SW) into a more extensive bus, which is only used when data must be transferred between different sets. Supply voltage of each sub-bus is adjustable and is set the lower the less traffic there is on the bus. The parallel transfer operation makes it possible to increase the transfer capacity of the bus structure without increasing it's clock frequency. Furthermore energy consumption can be reduced by dropping the supply voltage of the bus circuits so that the bus retains the transfer capacity needed.
    Type: Application
    Filed: December 12, 2003
    Publication date: August 5, 2004
    Applicant: Nokia Corporation
    Inventors: Jari Parviainen, Timo Hamalainen, Kimmo Kuusilinna