Patents by Inventor Jarkko Pietikäinen

Jarkko Pietikäinen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silane monomers and siloxane polymers for semiconductor optoelectronics
    Patent number: 7955660
    Abstract: A method for producing a polymer for semiconductor optoelectronics, comprising the steps of providing a monomer is produced having the formula: wherein: R1 is a hydrolysable group R2 is hydrogen, and R3 is a bridging linear or branched bivalent hydrocarbyl group, said monomer being produced by hydrosilylation of the corresponding starting materials, and homo- or copolymerizing the monomer to produce a polymer.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 7, 2011
    Assignee: Silecs Oy
    Inventors: Juha T. Rantala, Jyri Paulasaari, Jarkko Pietikäinen
  • Silane monomers and siloxane polymers for semiconductor optoelectronics
    Publication number: 20100136798
    Abstract: A method for producing a polymer for semiconductor optoelectronics, comprising the steps of providing a monomer is produced having the formula: wherein: R1 is a hydrolysable group R2 is hydrogen, and R3 is a bridging linear or branched bivalent hydrocarbyl group, said monomer being produced by hydrosilylation of the corresponding starting materials, and homo- or copolymerizing the monomer to produce a polymer.
    Type: Application
    Filed: September 30, 2009
    Publication date: June 3, 2010
    Inventors: Juha T. Rantala, Jyri Paulasaari, Jarkko Pietikäinen
  • Polyorganosiloxane dielectric materials
    Patent number: 7504470
    Abstract: A thin film comprising a composition obtained by polymerizing a monomer having the formula I: wherein: R1 is a hydrolysable group, R2 is a polarizability reducing organic group, and R3 is a bridging hydrocarbon group, to form a siloxane material. The invention also concerns methods for producing the thin films. The thin film can be used a low k dielectric in integrated circuit devices. The novel dielectric materials have excellent properties of planarization resulting in good local and global planarity on top a semiconductor substrate topography, which reduces or eliminates the need for chemical mechanical planarization after dielectric and oxide liner deposition.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 17, 2009
    Assignee: Silecs Oy
    Inventors: Juha T. Rantala, Jyri Paulasaari, Janne Kylmä, Turo T. Törmänen, Jarkko Pietikäinen, Nigel Hacker, Admir Hadzic