Patents by Inventor Jasjeet Singh

Jasjeet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160132913
    Abstract: A system and method contact a customer of an energy utility to solicit participation in an energy efficiency, sustainability, or reliability program. The system receives data pertaining to each customer, the data for each customer having a plurality of attributes pertaining to a customer descriptive characteristic, communications history, energy usage, or attitude. The data are normalized to a canonical form, and populated in a multivariate data model. Data in the model is clustered using a multivariate algorithm. Each cluster is assigned a utility customer segment, such as “Concerned Green” or “DIY”, that reflects the prevalent attributes. For each segment, the system determines a prospect subset of the customers most likely to participate in an offering pertaining to that segment according to a likelihood threshold. Finally, a prospect customer is contacted with an offering that may be customized according to the assigned customer segment.
    Type: Application
    Filed: April 9, 2015
    Publication date: May 12, 2016
    Inventors: Jasjeet Singh Hanjrah, Bipin Patwardhan, Sanghamitra Mitra, Nilendra Chaudhari
  • Patent number: 8477898
    Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 2, 2013
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
  • Publication number: 20110310942
    Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
  • Patent number: 7711855
    Abstract: In one implementation, a method includes obtaining a data entry from a user of a device, and obtaining a first time entry related to a first time zone. The first time entry and the first time zone are selected by a user of the device and the device converts the first time entry to a second time in a second time zone associated with a user of the device. The device then stores the data entry with the second time in the device. The method and device can thus be used to schedule a meeting in a selected local time in selected time zone, which is then converted to a local time in a time zone associated with the device.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: May 4, 2010
    Assignee: Siebel Systems, Inc.
    Inventors: Jasjeet Singh Thind, John Leo, Yoram Tal, Maria Kaval
  • Patent number: 7616074
    Abstract: Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 10, 2009
    Inventors: Dino Anthony Toffolon, Jasjeet Singh, Nacer Eddine Belabbes
  • Publication number: 20090002087
    Abstract: Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Dino Anthony Toffolon, Jasjeet Singh, Nacer Eddine Belabbes