Patents by Inventor Jaskaran Singh Bhatia

Jaskaran Singh Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library
    Patent number: 10651850
    Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sajal Mittal, Jaskaran Singh Bhatia, Rajeela Deshpande, Parvinder Kumar Rana, Nikhila C M, Abhishek Ghosh, Rahul Kataria
  • LOW VOLTAGE TOLERANT ULTRA-LOW POWER EDGE TRIGGERED FLIP-FLOP FOR STANDARD CELL LIBRARY
    Publication number: 20200067507
    Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.
    Type: Application
    Filed: March 25, 2019
    Publication date: February 27, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sajal Mittal, Jaskaran Singh Bhatia, Rajeela Deshpande, Parvinder Kumar Rana, Nikhila C M, Abhishek Ghosh, Rahul Kataria