Patents by Inventor Jaskirat Bindra

Jaskirat Bindra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357735
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar LALGUDI
  • Patent number: 10819325
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10748849
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Publication number: 20200036368
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Patent number: 10476490
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Publication number: 20190252309
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar LALGUDI
  • Patent number: 10276497
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat Bindra, Kumar Lalgudi
  • Publication number: 20190096799
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar Lalgudi
  • Publication number: 20180108388
    Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Jaskirat Bindra, Kumar Lalgudi