Patents by Inventor Jaskirat Bindra
Jaskirat Bindra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11239163Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: GrantFiled: July 28, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat Bindra, Kumar Lalgudi
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Patent number: 11201610Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: GrantFiled: October 8, 2020Date of Patent: December 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jaskirat Bindra, Kumar Lalgudi
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Publication number: 20210028776Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Inventors: Jaskirat Bindra, Kumar Lalgudi
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Publication number: 20200357735Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: ApplicationFiled: July 28, 2020Publication date: November 12, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat BINDRA, Kumar LALGUDI
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Patent number: 10819325Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: GrantFiled: October 2, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jaskirat Bindra, Kumar Lalgudi
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Patent number: 10748849Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: GrantFiled: April 29, 2019Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat Bindra, Kumar Lalgudi
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Publication number: 20200036368Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: ApplicationFiled: October 2, 2019Publication date: January 30, 2020Inventors: Jaskirat Bindra, Kumar Lalgudi
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Patent number: 10476490Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: GrantFiled: October 18, 2016Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jaskirat Bindra, Kumar Lalgudi
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Publication number: 20190252309Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat BINDRA, Kumar LALGUDI
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Patent number: 10276497Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: GrantFiled: September 27, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat Bindra, Kumar Lalgudi
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Publication number: 20190096799Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaskirat BINDRA, Kumar Lalgudi
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Publication number: 20180108388Abstract: Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.Type: ApplicationFiled: October 18, 2016Publication date: April 19, 2018Inventors: Jaskirat Bindra, Kumar Lalgudi