Patents by Inventor Jasmeet Singh Narang

Jasmeet Singh Narang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207527
    Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Inventors: Wonjun JUNG, Jasmeet SINGH NARANG, Tyrone HUANG, Christopher KLEMENT, Alan D. SMITH, Edward CHANG, John WUU
  • Patent number: 7199607
    Abstract: There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: April 3, 2007
    Assignee: Infineon Technologies AG
    Inventors: Ingo Volkening, Hong Lee Koo, Jasmeet Singh Narang, Jiaxiang Shi
  • Publication number: 20060132178
    Abstract: There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventors: Ingo Volkening, Hong Lee Koo, Jasmeet Singh Narang, Jiaxiang Shi
  • Patent number: 7057590
    Abstract: An LED array arrangement that reduces the number of control inputs needed to operate it is described. The reduction in the number of control pins is achieved through the use of logical ‘AND’ decoding and multiplexing of the control input signals.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: June 6, 2006
    Assignee: Infineon Technologies AG
    Inventors: Swee Hock Alvin Lim, Jasmeet Singh Narang