Patents by Inventor Jasmeet Singh Narula

Jasmeet Singh Narula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method, and computer program product for analyzing X-propagation failures in formal verification
    Patent number: 10031990
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The method may also include running a first target node and if the first target node is proven, run at least one additional target node until all target nodes are proven.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 24, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pradeep Goyal, Deepak Yadav, Jasmeet Singh Narula