Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.

Abstract: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, v, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave table is generated based on the sub-table by generating a plurality of multiplets that together form the interleave table. In addition, the sub-table may be generated based on the data block size and the offset vector by (i) rounding the data block size up to a nearest multiple of the length, x, of the offset vector to generate a modified block size, N?, and (ii) generating the sub-table of a size equal to N?/x.

Abstract: A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections between the plurality of reconfigurable component blocks; 3) determining from the P lists of required interconnections a minimum number, B, of data buses required to implement the P possible configurations for the defined function; 4) for each of the P possible configurations, determining the interconnections of each of the plurality of reconfigurable component blocks to each of the B buses; and 5) implementing programmable switches capable of coupling a first reconfigurable component block to a first bus only if required to implement at least one of the P possible configurations.

Abstract: A decoding process for decoding a received block of N systematic binary data samples or N systematic duobinary data samples using a maximum a posteriori probability (MAP) decoding algorithm. The decoding process calculates a set of four log-likelihood values using the corresponding forward state metric, reverse state metric, and branch metric values for each of N/2 pairs of systematic binary data or each of N/2 pairs of duobinary data in the received block. The decoding process also calculates, for each set of four log-likelihood values a delta value corresponding to the difference between the largest and the second largest of the four log-likelihood values in each set. The decoding process repeats for at least a second iteration. The decoding process is stopped based on a plurality of delta values calculated during two consecutive iterations.

Abstract: A software-defined radio (SDR) system comprising: 1) a reconfigurable baseband subsystem for supporting a plurality of wireless communication standards comprising a first plurality of reconfigurable context-based operation instruction set processors; and 2) a reconfigurable application subsystem for supporting a plurality of end-user applications comprising a second plurality of reconfigurable context-based operation instruction set processors. Each of the first and second pluralities of reconfigurable context-based operation instruction set processors comprises: i) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and ii) a programmable finite state machine that controls the reconfigurable data path, wherein the programmable finite state machine is capable of executing a plurality of instructions associated with a particular function.

Abstract: A system for cyclic redundancy check (CRC) calculations with modulo-2 multiplication is disclosed for repetitive CRC computations that optimizes processing efficiency and maximizes capacity. The resulting system results in the use of relatively fewer logical gates and conserves on power. The system receives a message ({right arrow over (m)}) including a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (?)}i). The system performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by: CRC ? ( m ? ) ? CRC ( ? i ? b ? i ? ? ? i ) .

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Abstract: An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated with the loop during a first iteration of the loop, storing first decoded instruction information associated with the first instruction during the first iteration of the loop, and using the stored first decoded instruction information during at least a second iteration of the loop without further fetching and decoding of the first instruction during the at least a second iteration of the loop.

Abstract: A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling the reconfigurable data path. The programmable finite state machine is capable of executing a first plurality of context-related instructions that are a first subset of the first instruction set.

Abstract: A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)}i). Each block ({right arrow over (b)}i) is of size (M) and is related to a unit vector ({right arrow over (e)}i). A summation operation on the blocks ({right arrow over (b)}i) given by CRC({right arrow over (b)})=?bi·CRC({right arrow over (e)}i) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)}i)) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.

Abstract: A reconfigurable Viterbi decoder comprising a reconfigurable data path and a programmable finite state machine that controls the reconfigurable data path. The reconfigurable data path comprises a plurality of reconfigurable functional blocks including: i) a reconfigurable branch metric calculation block; and ii) a reconfigurable add-compare-select and path metric calculation block. The programmable finite state machine executes a plurality of context-related instructions associated with the reconfigurable Viterbi decoder.

Abstract: A method for optimizing a software-defined radio system comprising a plurality of processors is provided. The method includes, for each of the plurality of processors, (i) providing an input burst comprising a first specified burst size, M, of input words to the processor for each of a plurality of configurations, each input word comprising an integer, and (ii) receiving from the processor an output burst comprising a second specified burst size, N, of output words generated by the processor based on the M input words for each of the configurations. An optimization factor is determined for each of the configurations based on the N output words generated by each processor for the configuration. An optimized configuration is identified from the plurality of configurations based on the optimization factor of each of the configurations.

Abstract: A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples while a second processing unit may be disabled. The number of processing units selected to decode the soft input data samples is determined by a data rate of the received soft input data samples. The reconfigurable turbo decoder also comprises N input data memories that store the received soft input data samples and N extrinsic information memories that store extrinsic information generated by the N processing units. Each of the N processing units is capable of reading from and writing to each of the N input data memories and each of the N extrinsic information memories.

Abstract: A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a?b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and ?1 and 2) the difference (a?b) multiplied by one of +1 and ?1.

Abstract: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, {right arrow over (v)}, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave table is generated based on the sub-table by generating a plurality of multiplets that together form the interleave table. In addition, the sub-table may be generated based on the data block size and the offset vector by (i) rounding the data block size up to a nearest multiple of the length, x, of the offset vector to generate a modified block size, N?, and (ii) generating the sub-table of a size equal to N?/x.

Abstract: A system for cyclic redundancy check (CRC) calculations with modulo-2 multiplication is disclosed for repetitive CRC computations that optimizes processing efficiency and maximizes capacity. The resulting system results in the use of relatively fewer logical gates and conserves on power. The system receives a message ({right arrow over (m)}) including a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (?)}i). The system performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by: CRC ? ( m ? ) ? CRC ( ? i ? b ? i ? ? ? i ) .

Abstract: A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)}i). Each block ({right arrow over (b)}i) is of size (M) and is related to a unit vector ({right arrow over (e)}i). A summation operation on the blocks ({right arrow over (b)}i) given by CRC({right arrow over (b)})=?bi·CRC({right arrow over (e)}i) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)}i)) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.

Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.

Abstract: A decoding process for decoding a received block of N systematic binary data samples or N systematic duobinary data samples using a maximum a posteriori probability (MAP) decoding algorithm. The decoding process calculates a set of four log-likelihood values using the corresponding forward state metric, reverse state metric, and branch metric values for each of N/2 pairs of systematic binary data or each of N/2 pairs of duobinary data in the received block. The decoding process also calculates, for each set of four log-likelihood values a delta value corresponding to the difference between the largest and the second largest of the four log-likelihood values in each set. The decoding process repeats for at least a second iteration. The decoding process is stopped based on a plurality of delta values calculated during two consecutive iterations.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).