Patents by Inventor Jasmina Vasiljevic
Jasmina Vasiljevic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960885Abstract: Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.Type: GrantFiled: April 11, 2022Date of Patent: April 16, 2024Assignee: Tenstorrent Inc.Inventors: Jasmina Vasiljevic, Ljubisa Bajic, Davor Capalija, Stanislav Sokorac
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Patent number: 11934897Abstract: Methods and systems for executing an application data flow graph using a network of computational nodes are disclosed. In specific examples, the network of computational nodes can be a network-on-chip for a multicore processor. One method includes transitioning first application data from a first source computational node to an intermediary computational node. The method can also include providing second application data, from a computation layer of the network of computational nodes, on the intermediary computational node. The method can also include multicasting the first application data in combination with the second application data from the intermediary computational node to at least two destination computational nodes. The first source computational node, the intermediary computational node, and the at least two destination computational nodes are all in the network of computational nodes.Type: GrantFiled: January 29, 2021Date of Patent: March 19, 2024Assignee: Tenstorrent Inc.Inventors: Jasmina Vasiljevic, Davor Capalija, Zahi Moudallal, Utku Aydonat, Joseph Chu, S. Alexander Chin, Ljubisa Bajic
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Patent number: 11829752Abstract: Processor cores using packet identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of packets using a set of packet identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent packet identifiers in the set of packet identifiers. In specific implementations the set of the operand identifiers represent packet identifiers in the set of packet identifiers in that a set of memories on the set of processing cores stores data values in common association with both the set of packets, and a set of operands identified by the set of operand identifiers. In specific implementations the set of operand identifiers and packet identifiers are unambiguously mapped to an underlying set of application datums of the complex computation.Type: GrantFiled: March 3, 2022Date of Patent: November 28, 2023Assignee: Tenstorrent Inc.Inventors: Davor Capalija, Ljubisa Bajic, Jasmina Vasiljevic
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Publication number: 20230325183Abstract: Methods and systems related to parallel computing using heterogenous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogenous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network, to facilitate the execution of the complex computation by the heterogenous set of computational nodes, and in response to the execution of the instructions.Type: ApplicationFiled: April 11, 2022Publication date: October 12, 2023Applicant: Tenstorrent Inc.Inventors: Jasmina Vasiljevic, Ljubisa Bajic, Davor Capalija, Stanislav Sokorac
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Publication number: 20230325160Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: ApplicationFiled: May 25, 2023Publication date: October 12, 2023Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230281155Abstract: Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Applicant: Tenstorrent Inc.Inventors: Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic, Ljubisa Bajic
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Patent number: 11734224Abstract: Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.Type: GrantFiled: September 28, 2020Date of Patent: August 22, 2023Assignee: Tenstorrent Inc.Inventors: Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic, Ljubisa Bajic
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Publication number: 20230259579Abstract: Methods and systems relating to reducing the number of computations required to execute an artificial neural network (ANN) are disclosed herein. A disclosed method includes: generating a summary of a set of data which is an input for a composite computation; executing a simplified composite computation, using the summary, to produce a simplified output; and executing a second simplified composite computation, using the simplified output, to produce a second simplified output which is a predictor. The second simplified composite computation is a simplification of a second composite computation. The composite computations are both part of a complex computation for the directed graph. The second composite computation depends on the composite computation in the directed graph. The method further includes suppressing, while executing the complex computation, a set of component computations from the second composite computation. The set of component computations are selected for suppression based on the predictor.Type: ApplicationFiled: January 31, 2022Publication date: August 17, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230236831Abstract: Processor cores using content object identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of content objects using a set of content object identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent content object identifiers in the set of content object identifiers. The content objects can be routed according to a named data networking (NDN) or content-centric networking (CCN) paradigm with the content object identifiers mentioned above serving as the names for the computation data being routed by the network.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Inventors: Davor Capalija, Ljubisa Bajic, Jasmina Vasiljevic, Yongbum Kim
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Patent number: 11709662Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: GrantFiled: November 5, 2021Date of Patent: July 25, 2023Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Patent number: 11693639Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: GrantFiled: November 5, 2021Date of Patent: July 4, 2023Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230196124Abstract: Methods and systems relating to reducing the number of computations required to execute an artificial neural network (ANN) are disclosed herein. The methods include a computer-implemented method conducted during an execution of an ANN. The method includes generating a set of execution data, generating a summary of a set of neural network data of the ANN, generating a summary of a set of execution data of the execution of the ANN, generating a prediction using the summary of the set of neural network data and the summary of the set of execution data, and executing a composite computation. The composite computation is required for the execution of the ANN. The method also includes suppressing a set of component computations of the composite computation. The set of suppressed component computations is at least partly determined by the prediction.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230146541Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Ahmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230143538Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Ahmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230041130Abstract: Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units.Type: ApplicationFiled: September 14, 2022Publication date: February 9, 2023Inventors: Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky, S. Alexander Chin, Ljubisa Bajic, Alex Cejkov, Milos Trajkovic
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Patent number: 11467846Abstract: Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor stack for the multicore processor can include a computation layer, for conducting computations using the processing cores in the multicore processor, with executable instructions for processing pipelines in the processing cores. The multicore processor stack can also include a network-on-chip layer, for connecting the processing cores in the multicore processor, with executable instructions for routers and network interface units in the multicore processor. The computation layer and the network-on-chip layer can be logically isolated by a network-on-chip overlay layer.Type: GrantFiled: July 29, 2020Date of Patent: October 11, 2022Assignee: Tenstorrent Inc.Inventors: Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky, S. Alexander Chin, Ljubisa Bajic
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Publication number: 20220245009Abstract: Methods and systems for the for executing an application data flow graph using a network of computational nodes are disclosed. In specific examples, the network of computational nodes can be a network-on-chip for a multicore processor. One method includes transitioning first application data from a first source computational node to an intermediary computational node. The method can also include providing second application data, from a computation layer of the network of computational nodes, on the intermediary computational node. The method can also include multicasting the first application data in combination with the second application data from the intermediary computational node to at least two destination computational nodes. The first source computational node, the intermediary computational node, and the at least two destination computational nodes are all in the network of computational nodes.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Applicant: Tenstorrent Inc.Inventors: Jasmina Vasiljevic, Davor Capalija, Zahi Moudallal, Utku Aydonat, Joseph Chu, S. Alexander Chin, Ljubisa Bajic
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Publication number: 20220188106Abstract: Processor cores using packet identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of packets using a set of packet identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent packet identifiers in the set of packet identifiers. In specific implementations the set of the operand identifiers represent packet identifiers in the set of packet identifiers in that a set of memories on the set of processing cores stores data values in common association with both the set of packets, and a set of operands identified by the set of operand identifiers. In specific implementations the set of operand identifiers and packet identifiers are unambiguously mapped to an underlying set of application datums of the complex computation.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Applicant: Tenstorrent Inc.Inventors: Davor Capalija, Ljubisa Bajic, Jasmina Vasiljevic
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Publication number: 20220100503Abstract: Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Applicant: Tenstorrent Inc.Inventors: Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic, Ljubisa Bajic
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Patent number: 11269628Abstract: Processor cores using packet identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of packets using a set of packet identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent packet identifiers in the set of packet identifiers. In specific implementations the set of the operand identifiers represent packet identifiers in the set of packet identifiers in that a set of memories on the set of processing cores stores data values in common association with both the set of packets, and a set of operands identified by the set of operand identifiers. In specific implementations the set of operand identifiers and packet identifiers are unambiguously mapped to an underlying set of application datums of the complex computation.Type: GrantFiled: June 15, 2020Date of Patent: March 8, 2022Assignee: Tenstorrent Inc.Inventors: Davor Capalija, Ljubisa Bajic, Jasmina Vasiljevic