Abstract: An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.

Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.

Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.

Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.

Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.

Abstract: An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.

Abstract: An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.

Abstract: An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.

Abstract: A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions indicate such mismatch correction may not improve performance.

Abstract: A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).

Abstract: A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions

Abstract: A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).

Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.

Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.

Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.

Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.

Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.