Patents by Inventor Jason A. Messier

Jason A. Messier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11415623
    Abstract: An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 16, 2022
    Assignee: Teradyne, Inc.
    Inventors: Jason A. Messier, Bryce M. Wynn, Ernest DiMicco
  • Patent number: 11221361
    Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 11, 2022
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, William Bowhers
  • Patent number: 11187745
    Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 30, 2021
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, Anja Deric
  • Publication number: 20210132143
    Abstract: An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Jason A. Messier, Bryce M. Wynn, Anja Deric
  • Publication number: 20210063474
    Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Inventors: Jason A. Messier, Bryce M. Wynn, William Bowhers
  • Publication number: 20200309849
    Abstract: An example test system includes power amplifier circuitry to force voltage or current to a test channel and one or more processing devices configured to control the power amplifier circuitry to comply with a compliance curve. The compliance curve relates output of the voltage to output of the current. According to the compliance curve, maximum current output increases as an absolute value of the voltage output increases.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Jason A. Messier, Bryce M. Wynn, Ernest DiMicco
  • Patent number: 10615230
    Abstract: An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Teradyne, Inc.
    Inventors: Jason A. Messier, Bradley A. Phillips, Kyle L. Klatka, Brian L. Massey, Peter J. D'Antonio, Anthony J. Suto
  • Publication number: 20190140032
    Abstract: An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.
    Type: Application
    Filed: March 27, 2018
    Publication date: May 9, 2019
    Inventors: Jason A. Messier, Bradley A. Phillips, Kyle L. Klatka, Brian L. Massey, Peter J. D'Antonio, Anthony J. Suto
  • Patent number: 8193956
    Abstract: A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions indicate such mismatch correction may not improve performance.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: June 5, 2012
    Assignee: Intersil Americas Inc.
    Inventor: Jason A. Messier
  • Patent number: 8144040
    Abstract: A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 27, 2012
    Assignee: Intersil Americas, Inc.
    Inventors: Jason A. Messier, Michael F. Lamenza
  • Publication number: 20110001645
    Abstract: A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).
    Type: Application
    Filed: March 30, 2010
    Publication date: January 6, 2011
    Applicant: Intersil Americas, Inc.
    Inventors: Jason A. Messier, Michael F. Lamenza
  • Publication number: 20110001644
    Abstract: A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions
    Type: Application
    Filed: April 27, 2010
    Publication date: January 6, 2011
    Applicant: Intersil Americas Inc.
    Inventor: Jason A. Messier