Patents by Inventor Jason A. Reid

Jason A. Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8273582
    Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: September 25, 2012
    Assignee: Crocus Technologies
    Inventors: Jean Pierre Nozieres, Jason Reid
  • Publication number: 20120225499
    Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.
    Type: Application
    Filed: May 10, 2012
    Publication date: September 6, 2012
    Applicant: CROCUS TECHNOLOGIES
    Inventors: Jean Pierre Nozieres, Jason Reid
  • Publication number: 20120008383
    Abstract: The present disclosure concerns a magnetic element to be written using a thermally-assisted switching write operation comprising a magnetic tunnel junction formed from a tunnel barrier being disposed between first and second magnetic layers, said second magnetic layer having a second magnetization which direction can be adjusted during a write operation when the magnetic tunnel junction is heated at a high threshold temperature; an upper current line connected at the upper end of the magnetic tunnel junction; and a strap portion extending laterally and connected to the bottom end of the magnetic tunnel junction; the magnetic device further comprising a bottom thermal insulating layer extending substantially parallel to the strap portion and arranged such that the strap portion is between the magnetic tunnel junction and the bottom thermal insulating layer. The magnetic element allows for reducing heat losses during the write operation and has reduced power consumption.
    Type: Application
    Filed: June 7, 2011
    Publication date: January 12, 2012
    Applicant: CROCUS TECHNOLOGY SA
    Inventors: Erwan Gapihan, Kenneth Mackay, Jason Reid
  • Publication number: 20110108937
    Abstract: Disclosed herein is a thermally-assisted magnetic tunnel junction structure including a thermal barrier. The thermal barrier is composed of a cermet material in a disordered form such that the thermal barrier has a low thermal conductivity and a high electric conductivity. Compared to conventional magnetic tunnel junction structures, the disclosed structure can be switched faster and has improved compatibility with standard semiconductor fabrication processes.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 12, 2011
    Applicant: CROCUS TECHNOLOGY SA
    Inventor: Jason Reid
  • Publication number: 20110008915
    Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 13, 2011
    Inventors: Jean Pierre Nozieres, Jason Reid
  • Patent number: 7622399
    Abstract: A method of forming a low dielectric constant structure. The method comprises providing at a first temperature a dielectric material having a first dielectric constant and a first elastic modulus, and curing the dielectric material by a thermal curing process, in which the material is heated to a second temperature by increasing the temperature at an average rate of at least 1° C. per second. As a result a densified, dielectric material is obtained which has a low dielectric constant.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: November 24, 2009
    Assignee: Silecs Oy
    Inventors: Jason Reid, Nigel Hackera, Nina Pirilä, Juha Rantala, William McLaughlin
  • Publication number: 20090278254
    Abstract: An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more.
    Type: Application
    Filed: December 1, 2008
    Publication date: November 12, 2009
    Inventors: Juha T. Rantala, Nigel Hacker, Jason Reid, William McLaughlin, Teemu T. Tormanen
  • Publication number: 20090072218
    Abstract: A phase change memory may be formed of a phase change material alloy that produces a higher threshold voltage and, in some cases, is operable at higher temperatures. For example, the formulation may include a poor metal, antimony, and at least one of tellurium or selenium.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Semyon Savransky, Ilya Karpov, Jason Reid
  • Publication number: 20070227878
    Abstract: A phase change memory including an ovonic threshold switch may be formed with reduced argon in the ovonic threshold switch. The presence of argon adversely impacts the performance of the ovonic threshold switch. Argon concentration can be reduced by depositing the phase change material for the ovonic threshold switch in a relatively low pressure argon environment to enable the argon pressure within said chamber to be reduced.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 4, 2007
    Inventors: Roger Hamamjy, Kuo-Wei Chang, Jason Reid
  • Publication number: 20070077779
    Abstract: A method for making an integrated circuit is disclosed as comprising depositing alternating regions of electrically conductive and dielectric materials on a substrate, wherein an area of dielectric material is formed by: a silane precursor having a fully or partially fluorinated first organic group comprising an unsaturated carbon-carbon double bond, the fully or partially fluorinated organic group bound to silicon in the silane precursor; forming from the silane precursor a hybrid organic-inorganic material having a molecular weight of at least 500 on a substrate; and increasing the molecular weight of the hybrid material by exposure to heat, electromagnetic radiation or electron beam so as to break the unsaturated carbon-carbon double bond and cross link via the fully or partially fluorinated organic group.
    Type: Application
    Filed: December 1, 2006
    Publication date: April 5, 2007
    Inventors: Juha Rantala, Jason Reid, T. Teemu Tormanen, Nungavram Viswanathan, Arto Maaninen
  • Publication number: 20060258146
    Abstract: A method for making an integrated circuit. An area of dielectric material is formed on a substrate by hydrolyzing a plurality of precursors to form a hybrid organic inorganic material. One of the precursors is a compound R1R2R3SiR4, wherein R1, R2, R3 are each independently aryl, a cross linkable group, or alkyl of 1-14 carbons, and wherein R4 is alkoxy, acyloxy, —OH or halogen. Also disclosed is a method for forming a hybrid organic inorganic layer on a substrate by hydrolyzing a tetraalkoxysilane, trialkoxysilane, trichlorosilane, dialkoxysilane, or dichlorosilane, with R1R2R4MR5, wherein R1, R2 and R4 are independently aryl, alkyl, alkenyl, epoxy or alkynyl, at least one of R1, R2 and R4 is fully or partially fluorinated, M is selected from group 14 of the periodic table, and R5 is either alkoxy, OR3 wherein R3 is alkyl of 1 to 10 carbons, or halogen.
    Type: Application
    Filed: July 20, 2006
    Publication date: November 16, 2006
    Inventors: Juha Rantala, Jason Reid, T. Tormanen, Nungavram Viswanathan
  • Publication number: 20060131753
    Abstract: An integrated circuit is provided comprising a substrate and discrete areas of electrically insulating and electrically conductive material, wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more and a dielectric constant of 3.0 or less. The integrated circuit can be made by a method comprising: providing a substrate; forming discrete areas of electrically insulating and electrically conductive material on the substrate; wherein the electrically insulating material is deposited on the substrate followed by heating at a temperature of 350° C. or less; and wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more after densification.
    Type: Application
    Filed: January 30, 2006
    Publication date: June 22, 2006
    Inventors: Juha Rantala, Jason Reid, Nungavram Viswanathan, T. Teemu Tormanen
  • Publication number: 20060057801
    Abstract: Thin films are disclosed that are suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by hydrolysis of two or more silicon compounds, which yield an at least partially cross-linked siloxane structure. The invention also concerns a method for producing such films by preparing siloxane compositions by hydrolysis of suitable reactants, by applying the hydrolyzed compositions on a substrate in the form of a thin layer and by curing the layer to form a film. In one example, a thin film comprising a composition is obtained by hydrolyzing a monomeric silicon compound having at least one hydrocarbyl radical, containing an unsaturated carbon-to-carbon bond, and at least one hydrolyzable group attached to the silicon atom of the compound with another monomeric silicon compound having at least one aryl group and at least one hydrolyzable group attached to the silicon atom of the compound to form a siloxane material.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 16, 2006
    Inventors: Juha Rantala, Jason Reid, Nungavram Viswanathan, T.Teemu Tormanen
  • Publication number: 20050164127
    Abstract: A method comprises depositing an organic material on a substrate; depositing additional material different from the organic material after depositing the organic material; and removing the organic material with a compressed fluid. Also disclosed is a method comprising: providing an organic layer on a substrate; after providing the organic layer, providing one or more layers of a material different than the organic material of the organic layer; removing the organic layer with a compressed fluid; and providing an anti-stiction agent with a compressed fluid to material remaining after removal of the organic layer.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 28, 2005
    Inventors: Jason Reid, Nungavaram Viswanathan
  • Publication number: 20050064726
    Abstract: A method of forming a low dielectric constant structure. The method comprises providing at a first temperature a dielectric material having a first dielectric constant and a first elastic modulus, and curing the dielectric material by a thermal curing process, in which the material is heated to a second temperature by increasing the temperature at an average rate of at least 1° C. per second. As a result a densified, dielectric material is obtained which has a low dielectric constant.
    Type: Application
    Filed: March 10, 2004
    Publication date: March 24, 2005
    Inventors: Jason Reid, Nigel Hacker, Nina Pirila, Juha Rantala, William McLaughlin
  • Publication number: 20050032357
    Abstract: An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 10, 2005
    Inventors: Juha Rantala, Nigel Hacker, Jason Reid, William McLaughlin, Teemu Tormanen
  • Patent number: 5729054
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5696018
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5622893
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: April 22, 1997
    Assignees: Texas Instruments Incorporated, California Institute of Technology
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa