Patents by Inventor Jason A. Viehland
Jason A. Viehland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11119766Abstract: Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.Type: GrantFiled: December 6, 2018Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Healy, Jason A. Viehland, Jeffrey H. Derby, Diana L. Orf
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Patent number: 10915477Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.Type: GrantFiled: June 25, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Chachi Ching, John A. Flanders, Michael J. Healy, Kevin J. Twilliger, Jason A. Viehland
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Patent number: 10831713Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: GrantFiled: October 24, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Publication number: 20200183686Abstract: Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Inventors: Michael J. Healy, Jason A. Viehland, Jeffrey H. Derby, Diana L. Orf
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Publication number: 20190317910Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: Chachi Ching, John A. Flanders, Michael J. Healy, Kevin J. Twilliger, Jason A. Viehland
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Patent number: 10387343Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.Type: GrantFiled: April 7, 2015Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Chachi Ching, John A. Flanders, Michael J. Healy, Kevin J. Twilliger, Jason A. Viehland
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Publication number: 20180052863Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: ApplicationFiled: October 24, 2017Publication date: February 22, 2018Inventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Patent number: 9858285Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: GrantFiled: May 4, 2015Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Patent number: 9836473Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: GrantFiled: October 3, 2014Date of Patent: December 5, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Patent number: 9684681Abstract: Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory.Type: GrantFiled: May 7, 2015Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason A. Viehland, John S. Yates, Jr.
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Publication number: 20160299858Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.Type: ApplicationFiled: April 7, 2015Publication date: October 13, 2016Inventors: Chachi Ching, John A. Flanders, Michael J. Healy, Kevin J. Twilliger, Jason A. Viehland
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Publication number: 20160098420Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node. A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data. An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: ApplicationFiled: May 4, 2015Publication date: April 7, 2016Inventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Publication number: 20160098439Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for hardware acceleration are presented. A plurality of computational nodes for processing data is provided, each node performing a corresponding operation for data received at that node, A metric module is used to determine a compression benefit metric pertaining to performance of the corresponding operations of one or more computational nodes with recompressed data, An accelerator module recompresses data for processing by the one or more computational nodes based on the compression benefit metric indicating a benefit gained by using the recompressed data. A distribution function may be used to distribute data among a plurality of nodes.Type: ApplicationFiled: October 3, 2014Publication date: April 7, 2016Inventors: Garth A. Dickie, Michael Sporer, Jason A. Viehland
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Publication number: 20150234871Abstract: Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory.Type: ApplicationFiled: May 7, 2015Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Jason A. Viehland, John S. Yates, JR.
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Patent number: 9087095Abstract: Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory.Type: GrantFiled: June 21, 2012Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Jason A. Viehland, John S. Yates, Jr.
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Publication number: 20130346428Abstract: Database processing using columns to present to a processing unit decompressed column data without changing the underlying row-based database architecture. For some embodiments, a database accelerator is used to efficiently process the columns of a database and output tuples to a processing unit's memory, such that the columns can be quickly processed (with the advantages of a column-based architecture) to create tuples of requested data, but without having to depart from a row-based architecture at the processing unit level or having decompressed data scattered throughout the processing unit's memory.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason A. Viehland, John S. Yates, JR.