Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.

Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.

Abstract: The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.

Abstract: The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.

Abstract: A two-step etching process is used to form the top electrode for a magnetoresistive device. The level of isotropy is different for each of the two etching steps, thereby providing advantages associated with isotropic etching as well as more anisotropic etching. The level of isotropy is controlled by varying power and pressure during plasma etching operations.

Abstract: A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Abstract: A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.

Abstract: A nearly balanced synthetic antiferromagnetic (SAF) structure that can be advantageously used in magnetoelectronic devices such as a magnetoresistive memory cell includes two ferromagnetic layers and an antiferromagnetic coupling layer separating the two ferromagnetic layers. The SAF free layer has weakly coupled regions formed in the antiferromagnetic coupling layer by a treatment such as annealing, layering of the antiferromagnetic coupling layer, or forming the antiferromagnetic coupling layer over a roughened surface of a ferromagnetic layer. The weakly coupled regions lower the flop field of the SAF free layer in comparison to untreated SAF free layers. The SAF flop is used during the write operation of such a structure and its reduction results in lower power consumption during write operations and correspondingly increased device performance.

Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.

Abstract: A magnetoresistive tunneling junction memory cell comprises a magnetoresistive tunneling barrier (16), a bit magnetic region (15), a reference magnetic region (17), and current lines (20, 30) for inducing an applied magnetic field in the bit and reference magnetic regions. The bit magnetic region has a bit magnetic moment (43, 40,1425, 1625, 1950, 2315) that has a polarity in a bit easy axis (59, 1435) when there is no applied magnetic field. The tunneling barrier and the bit and reference magnetic regions form a magnetoresistive tunneling junction device (10, 72, 73, 74, 75, 76). In some implementations (73, 74, 75), the reference magnetic region has a reference magnetic moment (40, 1430, 1440, 1920, 1925) that is non-parallel to the bit easy axis. In other implementations (76), the reference magnetic region has a magnetization vortex (2310) with a net reference magnetic moment that is essentially zero.

Abstract: A magnetoresistive tunneling junction memory cell (10) including a pinned ferromagnetic region (17) having a magnetic moment vector (47) fixed in a preferred direction in the absence of an applied magnetic field wherein the pinned ferromagnetic region has a magnetic fringing field (96), an electrically insulating material positioned on the pinned ferromagnetic region to form a magnetoresistive tunneling junction (16), and a free ferromagnetic region (15) having a magnetic moment vector (53) oriented in a position parallel or anti-parallel to that of the pinned ferromagnetic region wherein the magnetic fringing field is chosen to obtain a desired switching field.

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180°. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Abstract: A scalable magnetoresistive tunneling junction memory cell comprising a fixed ferromagnetic region having a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, an electrically insulating material positioned on the fixed ferromagnetic region to form a magnetoresistive tunneling junction, and a free ferromagnetic region having a magnetic moment vector oriented in a position parallel or anti-parallel to that of the fixed ferromagnetic region. The free ferromagnetic region includes N ferromagnetic layers that are anti-ferromagnetically coupled, where N is an integer greater than or equal to two. The number N of ferromagnetic layers can be adjusted to increase the effective magnetic switching volume of the MRAM device.

Abstract: A magnetoelectronics element (40) is provided that is comprised of a first magnetic layer (42), a first tunnel barrier layer (44) on the first magnetic layer (42), a second magnetic layer (46) on the first tunnel barrier layer (44) and a stressed over-layer (48) on the second magnetic layer (46), which is configured to alter a switching energy barrier of the second magnetic layer (46).