Patents by Inventor Jason B. Emery

Jason B. Emery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for address-mapped control of field programmable gate array (FPGA) via ethernet
    Patent number: 10225230
    Abstract: A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 5, 2019
    Assignee: Raytheon Company
    Inventors: Brandon H. Daugherty, Jason B. Emery, Brian D. Sirois, Bradley D. Staal, Paul J. Lewis, Michael S. Mitchener
  • SYSTEM AND METHOD FOR ADDRESS-MAPPED CONTROL OF FIELD PROGRAMMABLE GATE ARRAY (FPGA) VIA ETHERNET
    Publication number: 20180234383
    Abstract: A method includes receiving, at a field programmable gate array (FPGA), one or more Ethernet packets of a message including control or status information associated with the FPGA. The method also includes determining, by the FPGA, a payload of each packet by removing at least one Ethernet header from the packet. The method further includes removing, by the FPGA, a User Datagram Protocol (UDP) header from each packet and determining UDP header metadata. The method also includes converting, by the FPGA based on the UDP header metadata, the packets to a read or write message associated with one or more registers of the FPGA. In addition, the method includes performing, by the FPGA, a read or write of the one or more registers of the FPGA according to the read or write message.
    Type: Application
    Filed: December 14, 2016
    Publication date: August 16, 2018
    Inventors: Brandon H. Daugherty, Jason B. Emery, Brian D. Sirois, Bradley D. Staal, Paul J. Lewis, Michael S. Mitchener