Abstract: The present disclosure includes systems and methods for determining candidates for clinical trials from unstructured clinical trial protocols associated with the clinical trial and medical records of patients based on machine learning, natural language processing or both. The systems and methods of the present disclosure can extract tokens from unstructured clinical trial protocols based on Natural Language Processing (NLP) and determine clinical trial criteria. The systems and methods of the present disclosure can determine clinical indications from the medical data associated with the patients using natural language processing and determine whether the clinical indications match the clinical trial criteria and determine a probability that the patients meet the clinical trial criteria based on a crosswalk matching and determine candidates for clinical trial from the patients based on the determined probability.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.

Abstract: A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct.

Abstract: An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g1i and g2i, and the fanout references of g1i and g2i are provided to a controllable multiplexer set to output g1i. Upon determining nonequivalence of g2i, of failing to proved equivalence, the multiplexer is switched to output the g1i fanout reference, thus undoing the incremental speculative merge.

Abstract: Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.

Abstract: Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable.

Abstract: Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.

Abstract: An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g1i and g2i, and the fanout references of g1i and g2i are provided to a controllable multiplexer set to output g1i. Upon determining nonequivalence of g2i, of failing to proved equivalence, the multiplexer is switched to output the g1i fanout reference, thus undoing the incremental speculative merge.

Abstract: Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.

Abstract: Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first set of variables are identified that support the selected variable. Then a second set of variables is identified that have overlapping support of the first set of variables. The second set of variables is a partition suitable for use in determining an overapproximation of the reachable states of the selected variable.

Abstract: A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.

Abstract: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.

Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

Abstract: A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

Abstract: A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.

Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more targets from the first target set and the structural product extraction is recursed for one or more next-state functions of a subset of the one or more registers. A sum-of-products form is recursed from the structural product extraction for one or more next-state functions of a subset of the one or more registers and a product-of-sums form of a result of the second recursing is decomposed to generate a decomposition of the product-of-sums form. The decomposition of the product-of-sums form is synthesized into a second target set and a subset of the second target set to recursively decompose is chosen.