Patents by Inventor Jason Bessette

Jason Bessette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to write modified cache data to a backing store while retaining write permissions
    Patent number: 9311241
    Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Robert Chappell, Zhongying Zhang, Jason Bessette
  • Deterministic clock crossing
    Patent number: 9285826
    Abstract: Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Stanley Steve Kulick, Erin Francom, Jason Bessette
  • DETERMINISTIC CLOCK CROSSING
    Publication number: 20130326205
    Abstract: Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.
    Type: Application
    Filed: December 22, 2011
    Publication date: December 5, 2013
    Inventors: Stanley Steve Kulick, Erin Francom, Jason Bessette