Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

Abstract: Described herein are transistor devices formed using perovskite gate dielectrics. In one example, a transistor includes a high-k perovskite dielectric material between a gate electrode and a thin film semiconductor channel. In another example, four-terminal transistor includes a semiconductor channel, a gate stack that includes a perovskite dielectric layer on one side of the channel, and a body electrode on an opposite side of the channel. The body electrode adjusts a threshold voltage of the transistor.

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

Abstract: Capacitors with a carbon-based electrode layer in contact with a ferroelectric insulator. The insulator may be a perovskite oxide. Low reactivity of the carbon-based electrode may improve stability of a ferroelectric capacitor. A carbon-based electrode layer may be predominantly carbon and have a low electrical resistivity. A carbon-based electrode layer may be the only layer of an electrode, or it may be a barrier between the insulator and another electrode layer. Both electrodes of a capacitor may include a carbon-based electrode layer, or a carbon-based electrode layer may be included in only one electrode.