Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract: Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced horizontal positions of an IC; providing a cross-couple region of a gate of the plurality of gates, the cross-couple region including a portion of the gate extending from a first horizontal position of the horizontal positions to a second horizontal position of the horizontal positions; and providing at least one of the plurality of gates with an overlap of first and second segments of the at least one gate, the first and second segments being designated to be decomposed using different colors.