Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Abstract: A positive electrode active material may include a compound represented by formula 1 or formula 2: Li(1.333?0.667x?y)Mn(0.667?0.333x)NixA(y?a)MaO2 (1), Li(1.333?0.667x?z?a)Mn(0.667?0.333x?0.5y)Ni(x?0.5y+z)A(y+a?b)MbO2 (2). A is Co, Cr, or a combination thereof, M is W+6, Ta+5, V+5, or a combination thereof, 0<x<0.5, 0<y<0.333, 0<x<0.04, 0<x?0.5y+z<0.5, 0<y+a?b<0.333, and 0<b<0.04.

Abstract: A positive electrode active material may include a compound represented by formula 1 or formula 2: Li1.10Mn0.52Ni(0.38-x)A(x-a)MaO2 (1), Li1.12Mn0.51Ni(0.37-x)A(x-a)MaO2 (2). A is Co, Cr, or a combination thereof, M is W+6, Ta+5, V+5, or a combination thereof, 0<x<0.1, 0<a<0.04, and 3.8<average oxidation state of Mn ion<4.0.

Abstract: An example of a surface cleaning head may include a main body, a neck pivotally coupled to the main body, a stabilizer, and a linkage pivotally coupled to the main body and the stabilizer. The linkage may be configured to cause the stabilizer to transition between an extended position and a retracted position in response to a pivotal movement of the neck.

Abstract: Three-dimensional meshes and three-dimensional casings for thermal ground planes are disclosed. These three-dimensional meshes and three-dimensional casings can create a vapor core that has structural resiliency positive or negative pressure differential between the vapor space and external conditions. A thermal ground plane is disclosed that includes a first casing that is substantially planar and a second casing. The outer periphery of the first casing and the outer periphery of the second casing are bonded together to form a hermetic seal. The second casing may be deformed to create a vapor support structure within the thermal ground plane that includes a plurality of deformed portions (or rough pillars). A working fluid may be disposed within the first casing and the second casing. Permeable wicks may also be disposed on an inner surface of the first casing and/or the second casing for liquid transport that is disposed between the first casing and the second casing.

Abstract: A process for charging a discharged electrochemical cell includes applying a voltage bias to the discharged electrochemical cell; and illuminating the cathode, the anode, or both the cathode and the anode with light having a narrow band of wavelengths corresponding to the respective band gaps of the electrode active materials.

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

Abstract: A low parasitic inductance power module having staggered, interleaving busbars, including: at least one base extending a long a length direction, the base having at least one current input busbar and at least one current output busbar, the current input busbar and the current out busbar being formed with a plurality of interdigitated contact terminals, respectively; a first unit comprising a first circuit base portion disposed on the base along the width direction, on the first circuit base portion being disposed a plurality of first power devices; and a second unit, whereby when current flows through the units and the individual interdigitated contact terminals, individual inductances produced thereby are cancelled with each other, whereby overall parasitic inductance of the power module is reduced.

Abstract: A low parasitic inductance power module featuring staggered, interleaving conductive members, including: at least one base extending in a length direction, at least one input bus-bar and at least one output bus-bar being disposed on the base; a first unit including a first circuit base portion disposed on the base along the width direction, a plurality of first power devices being disposed on the first circuit base portion, each of the first power devices having paralleled first current input ends and paralleled first current output ends; the first current input ends or the current output ends being conductively connected to the first circuit base portion; and a second unit. The units are serially connected to the bus-bars via staggered, interleaving input conductive members and output conductive members whereby individual inductances generated are mutually counteracted, thus reducing the overall parasitic inductance.

Abstract: A power module includes two power input terminals, two main substrates, a plurality of first switches, a plurality of second switches, and a bridge main unit. The bridge main unit is across the two main substrates, and includes a first bridge subunit and a second bridge subunit. Each of the first bridge subunit and the second bridge subunit includes a first conducting region on a bottom surface, and a second conducting region and a third conducting region on a top surface. The first conducting region transmits a current signal of a current path of a switch circuit formed by the power input terminals, the first switches, and the second switches. The second conducting region is connected to the control terminals of the first switches and the second switches. The third conducting region is connected to the output terminals of the first switches and the second switches.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: A low parasitic inductance power module featuring staggered interleaving conductive members, including: at least one base extending in a length direction; a substrate on which at least one input bus bar and at least one output bus bar are provided; a first unit including a first circuit base portion disposed on the base in a width direction, a plurality of first power devices being disposed on the first circuit base portion, each first power device having a first current input end and a first current output end which are parallel connected, the first current input end or the first current output end being conducted to the first circuit base portion; and a second unit. The units are serially-connected to the bus bars via input conductive members and output conductive members arrayed in a staggered interleaving mode, whereby to create individual inductances counteracting with each other, reducing overall parasitic inductance.

Abstract: A thin aluminum film substrate and microarrays thereof including a substrate and a thin film of aluminum deposited on the substrate for surface plasmon resonance analysis. Methods of forming the thin aluminum film substrate and microarrays including providing a substrate, using electron-beam physical vapor deposition (EBPVD) to deposit a thin film of Al on a surface of the substrate. Also disclosed are methods of detecting an analyte, wherein a functionalized surface of the thin aluminum film includes a biomolecule and the methods include applying a sample including the analyte to the thin aluminum film substrate, and using surface plasmon resonance (SPR) spectroscopy to detect molecular interactions between the biomolecule and the analyte at a surface of the thin aluminum film substrate. In some examples, an unmodified Al film with an Al2O3 layer is effective in enriching phosphorylated peptides. In some examples, a coating of an ionic polymer is used to analyze charged-based interactions of biomolecules.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A motor control device with built-in shunt resistor and power transistor is disclosed, comprising a high-thermally conductive substrate; an electrically conductive circuit which is thermo-conductively installed on the high-thermally conductive substrate and includes a first thermal connection pad portion and a second thermal connection pad portion mutually spaced apart; a high power transistor conductively connected to the electrical conducive circuit; and a shunt resistor conductively connected to the high power transistor, respectively including a body whose thermal expansion coefficient is greater than that of the high-thermally conductive substrate, as well as a pair of welding portions extending from the body, in which the body has a prescribed width, and the width of the welding portion is greater than the prescribed width, and the body and the high-thermally conductive substrate are spaced apart such that, upon welding the welding portion to the first thermal connection pad portion and the second therm

Abstract: A motor control device with built-in shunt resistor and power transistor is disclosed, comprising a high-thermally conductive substrate; an electrically conductive circuit which is thermo-conductively installed on the high-thermally conductive substrate and includes a first thermal connection pad portion and a second thermal connection pad portion mutually spaced apart; a high power transistor conductively connected to the electrical conducive circuit; and a shunt resistor conductively connected to the high power transistor, respectively including a body whose thermal expansion coefficient is greater than that of the high-thermally conductive substrate, as well as a pair of welding portions extending from the body, in which the body has a prescribed width, and the width of the welding portion is greater than the prescribed width, and the body and the high-thermally conductive substrate are spaced apart such that, upon welding the welding portion to the first thermal connection pad portion and the second therm

Abstract: A tape applicator for applying tape to seal a case is disclosed wherein the pressure applied to the top of the case may be significantly reduced by activating an actuator at the appropriate time to lift the application mechanism or assembly and the cut-off mechanism away from the case being sealed.

Abstract: A printed circuit board with built-in vertical heat dissipation ceramic block, and an electrical assembly are disclosed. The electrical assembly includes the board and a plurality of electronic components. The printed circuit boards includes a dielectric material layer defining at least one through hole, at least one ceramic block corresponding to the through hole, at least one fixing portion for joining the ceramic block to the through hole of the dielectric material layer, a metal circuit layer provided on upper surfaces of the dielectric material layer and the ceramic block, and a high thermal conductivity layer provided on lower surfaces of the dielectric material layer and the ceramic block. The printed circuit board allows the location and size of the ceramic block to be modified according to requirements, so as to implement complicated circuit designs, achieve good effect of thermal conduction, control thermal conduction path, and reduce manufacturing cost.

Abstract: A tape applicator for applying tape to seal a case is disclosed wherein the pressure applied to the top of the case may be significantly reduced by activating an actuator at the appropriate time to lift the application mechanism or assembly and the cut-off mechanism away from the case being sealed