Abstract: A thin aluminum film substrate and microarrays thereof including a substrate and a thin film of aluminum deposited on the substrate for surface plasmon resonance analysis. Methods of forming the thin aluminum film substrate and microarrays including providing a substrate, using electron-beam physical vapor deposition (EBPVD) to deposit a thin film of Al on a surface of the substrate. Also disclosed are methods of detecting an analyte, wherein a functionalized surface of the thin aluminum film includes a biomolecule and the methods include applying a sample including the analyte to the thin aluminum film substrate, and using surface plasmon resonance (SPR) spectroscopy to detect molecular interactions between the biomolecule and the analyte at a surface of the thin aluminum film substrate. In some examples, an unmodified Al film with an Al2O3 layer is effective in enriching phosphorylated peptides. In some examples, a coating of an ionic polymer is used to analyze charged-based interactions of biomolecules.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: A tape applicator for applying tape to seal a case is disclosed wherein the pressure applied to the top of the case may be significantly reduced by activating an actuator at the appropriate time to lift the application mechanism or assembly and the cut-off mechanism away from the case being sealed.

Abstract: A tape head or tape applicator applies low impact to the leading face of the incoming carton and low pressure to the top of the carton and a higher pressure to wipe down the tape onto the rear or trailing face of the case by increasing the tension in the spring driving the wipe down and a high cutting force to the cut-off mechanism for fast response of the cut-off mechanism by increasing the tension in the spring driving the cut-off mechanism.

Abstract: A tape applicator for applying tape to seal a case is disclosed wherein the pressure applied to the top of the case may be significantly reduced by activating an actuator at the appropriate time to lift the application mechanism or assembly and the cut-off mechanism away from the case being sealed

Abstract: Disclosed are apparatuses and methods for an apparatus that has a flexible mounting substrate, one or more flexible photovoltaic modules attached to the flexible mounting substrate, one or more inverters attached to the flexible mounting substrate and electrically connected to the one or more flexible photovoltaic modules, a flexible electrical conduit electrically connected to the one or more inverters and to the one or more flexible photovoltaic modules, a plurality of mounting features, and a plurality of flexible connectors that extend between the flexible mounting substrate and one corresponding mounting feature, that is configured to be positioned above a structure and secured to the structure without penetrating roofing of the structure.

Abstract: A magnetron sputtering system comprising a vacuum processing chamber having a chamber shield, a magnetron assembly, and a substrate, the magnetron assembly comprising a permanent magnetic assembly and an electromagnetic coil assembly, a first impedance circuit coupled between a power supply and the electromagnetic coil assembly, the first impedance circuit comprising a first resistor and a first capacitor, and a second impedance circuit having a second resistor and a second capacitor, and coupled between the substrate and a susceptor.

Abstract: A wireless image transmission device includes an image processing main body; an image display unit electrically connected to the image processing main body; a first switching unit electrically connected to between the image processing main body and the image display unit; an image shooting control unit electrically connected to the first switching unit; and a wireless transmission unit electrically connected to the image shooting control unit. With these arrangements, images to be wirelessly transmitted from the wireless image device need not be converted in file type, so that the wireless image transmission device can have high transmission efficiency and simplified overall configuration to overcome the drawback of complicated configuration in the prior art wireless image transmission device.

Abstract: A wireless image transmission device includes an image processing main body; an image display unit electrically connected to the image processing main body; a first switching unit electrically connected to between the image processing main body and the image display unit; an image shooting control unit electrically connected to the first switching unit; and a wireless transmission unit electrically connected to the image shooting control unit. With these arrangements, images to be wirelessly transmitted from the wireless image device need not be converted in file type, so that the wireless image transmission device can have high transmission efficiency and simplified overall configuration to overcome the drawback of complicated configuration in the prior art wireless image transmission device.

Abstract: In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.

Abstract: A wireless image shooting device includes a main body and a controlling display module. The main body includes a first central processing unit (CPU), a first wireless transmission unit, a first memory unit and an image shooting unit. The controlling display module includes a second CPU, a second wireless transmission unit, a second memory unit and a touch display unit. When the controlling display module is connected to the main body, data is transmitted between the first and the second CPU via cables; and when the controlling display module is separated from the main body, data is wirelessly transmitted between the first and the second wireless transmission unit. With these arrangements, the main body can be wirelessly controlled by the controlling display module to shoot images, so that the wireless image shooting device has increased functionality.

Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.

Abstract: In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data frame comprises a first data set; embedding a first instruction into the compressed bitstream to load the first data frame into a first row of configuration memory of the PLD at an address associated with the first data frame; identifying a second data frame in the uncompressed bitstream, wherein the second data frame comprises the first data set; and embedding a second instruction into the compressed bitstream to load the first data frame into a second row of the configuration memory at an address associated with the second data frame.

Abstract: Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration memory cells and at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells (e.g., identified as a defective memory cell). An address shift register within the device is adapted to provide programming signals to the plurality of configuration memory cells via wordlines. A data shift register within the device is adapted to provide configuration data to the plurality of configuration memory cells via bitlines. The data shift register is further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.

Abstract: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.

Abstract: Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.

Abstract: A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.