Patents by Inventor Jason Chien

Jason Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538740
    Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, Yuh-Harng Chien, J K Ho
  • Publication number: 20220017614
    Abstract: An anti-IL6 agent that blocks binding of IL-6 to IL-6 receptor, for example, an anti-IL6 antibody comprising a heavy chain variable region of SEQ ID NO:99 and a light chain variable region of SEQ ID NO:97, is useful in the treatment or prevention of infection of a human with SARS-CoV-1 and/or SARS-CoV-2.
    Type: Application
    Filed: March 30, 2021
    Publication date: January 20, 2022
    Inventors: Katia Boven, Jason Chien, Magda Opsomer, Brian Woodfall
  • Patent number: 11227852
    Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: January 18, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
  • Patent number: 11081429
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Publication number: 20210111103
    Abstract: A packaged semiconductor device includes a leadframe including a finger pad(s) that is integrated, and spans a finger pad area including a width narrower than its length. A first portion of the finger pad area provides a die support area. A second portion of the finger pad area provides a wire bond area including first and second wire bond pads on a first and second side of the die support area. One of the wire bond pads further includes a lead terminal integrally connected. The IC die has a top side with bond pads and a back side having a non-electrically conductive die attach material attached to the die support area. Bond wires extend from the bond pads to the first and second wire bond pads. A mold compound encapsulates the packaged semiconductor device leaving exposed at least the lead terminal on a bottom side of the packaged semiconductor device.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventors: Jason Chien, J K Ho, Yuh-Harng Chien
  • Publication number: 20210020549
    Abstract: A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Jason CHIEN, Yuh-Harng CHIEN, J K HO
  • Publication number: 20200251440
    Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Patent number: 10629562
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
  • Publication number: 20190206828
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 4, 2019
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Publication number: 20170327595
    Abstract: Provided are therapeutic, diagnostic, and prognostic methods for disease, including diseases associated with fibrosis and cancer using agents that bind to, inhibit, and/or detect lysyl oxidase-like 2 (LOXL2), and agents, compositions, kits, assay systems, and devices for use with such methods.
    Type: Application
    Filed: January 26, 2017
    Publication date: November 16, 2017
    Inventors: Jeffrey D. Bornstein, Joanne I. Adamkewicz, Victoria Smith, Susan K. Lyman, Jason Chien, Xiaoming Li, Lixin Shao
  • Publication number: 20170269085
    Abstract: The present disclosure provides an assay to detect and/or quantify circulating lysyl oxidase-like 2 (LOXL2) polypeptides in an individual. The assay is useful in diagnostic and prognostic applications, which are also provided.
    Type: Application
    Filed: December 1, 2016
    Publication date: September 21, 2017
    Inventors: Victoria Smith, Joanne I. Adamkewicz, Susan K. Lyman, Jason Chien, Xiaoming Li, Lixin Shao, Jeffrey D. Bornstein
  • Publication number: 20140206017
    Abstract: The present disclosure provides an assay to detect and/or quantify circulating lysyl oxidase-like 2 (LOXL2) poly-peptides in an individual. The assay is useful in diagnostic and prognostic applications, which are also provided.
    Type: Application
    Filed: June 1, 2012
    Publication date: July 24, 2014
    Inventors: Victoria Smith, Joanne I. Adamkewicz, Susan K. Lyman, Jason Chien, Xiaoming Li, Lixin Shao, Jeffrey D. Bornstein
  • Publication number: 20140120102
    Abstract: Provided are therapeutic, diagnostic, and prognostic methods for disease, including diseases associated with fibrosis and cancer using agents that bind to, inhibit, and/or detect lysyl oxidase-like 2 (LOXL2), and agents, compositions, kits, assay systems, and devices for use with such methods.
    Type: Application
    Filed: October 30, 2013
    Publication date: May 1, 2014
    Applicant: Gilead Sciences, Inc.
    Inventors: Jeffrey D. BORNSTEIN, Joanne I. ADAMKEWICZ, Victoria SMITH, Susan K. LYMAN, Jason CHIEN, Xiaoming LI, Lixin SHAO
  • Publication number: 20120309020
    Abstract: The present disclosure provides an assay to detect and/or quantify circulating lysyl oxidase-like 2 (LOXL2) polypeptides in an individual. The assay is useful in diagnostic and prognostic applications, which are also provided.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 6, 2012
    Applicant: Gilead Biologics, Inc.
    Inventors: Victoria Smith, Joanne I. Adamkewicz, Susan K. Lyman, Jason Chien, Xiaoming Li, Lixin Shao, Jeffrey D. Bornstein
  • Patent number: 6974749
    Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: December 13, 2005
    Assignee: Mosel Vitelic, Inc.
    Inventors: Shih-Chi Lai, Yifu Chung, Yi-Chuan Yang, Jen-Chieh Chang, Jason Chien-Sung Chu, Chun-De Lin
  • Publication number: 20040203217
    Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.
    Type: Application
    Filed: October 1, 2003
    Publication date: October 14, 2004
    Applicant: MOSEL VITELIC, INC.
    Inventors: Shih-Chi Lai, Yifu Chung, Yi-Chuan Yang, Jen-Chieh Chang, Jason Chien-Sung Chu, Chun-De Lin
  • Patent number: 6326320
    Abstract: A method for forming oxide layer on conductor plug of trench structure is proposed. The invention includes following essential steps: First, provide a substrate where a trench locates inside the substrate, herein the trench is partly filled by a conductor plug. Second, forms a plasma enhanced tetraethyl-orthosilicate layer on the substrate, herein the plasma enhanced tetraethyl-orthosilicate layer also fills the trench and covers the conductor plug. Finally, removes the plasma enhanced tetraethyl-orthosilicate layer until the substrate is not covered by the plasma enhanced tetraethyl-orthosilicate layer, herein the conductor plug still is covered by the plasma enhanced tetraethyl-orthosilicate layer. Additional, advantages of application of plasma enhanced tetraethyl-orthosilicate layer comprise compacted structure and high deposit rate.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: December 4, 2001
    Assignee: Mosel Vitelic Inc.
    Inventors: Yi-Chuan Yang, Jason Chien-Song Chu, Mike Wen-Jeh Su