Abstract: Message translation systems and methods are provided. In one embodiment, a method for translating messages comprises reading a first sequence of one or more message elements from a first interface, wherein the message elements are structured based on a first protocol; converging on a message mapping node based on the first sequence of one or more message elements, wherein the message mapping node is defined by a protocol metadata schema; performing one or more conversion operations on the first sequence of one or more message elements to construct a second sequence of one or more message elements, wherein the one or more conversion operations are based on the message mapping node; and writing the second sequence of one or more message elements to a second interface.

Abstract: System and methods for satellite payload application development are provided. A method for developing embedded processing systems comprises selecting a hardware layer configuration; and developing an interfacing software stack providing services from one or more of an infrastructure services layer, a bus abstraction layer, a device abstraction layer, and a peripheral device driver layer through one or more standard function calls.

Abstract: A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based in part on the measured environmental condition. The fault tolerance of the on-board processing system may be reconfigured based in part on the measured environmental condition.

Abstract: An improved system and method for dynamically optimizing the performance and reliability of redundant processing systems (e.g., for use in space applications) are disclosed. As one example, a Field Programmable Gate Array (FPGA) that includes a plurality of processors is disclosed. Based on mission specific modes or environmental conditions, the processing system can dynamically and safely transition between the high performance of, for example, a general purpose, quad Symmetric Multiprocessor (SMP) and the high reliability of a redundant set of processors (e.g., Triple Modular Redundancy system). This architecture allows the use of a single FPGA with multiple processors to take advantage of the maximum processing throughput available when sufficient mission conditions are met, and can also safely transition to a lower throughput, high reliability mode when needed.

Abstract: An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.