Patents by Inventor Jason Coppens

Jason Coppens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9167058
    Abstract: A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 20, 2015
    Assignee: XILINX, INC.
    Inventors: Paul Gresham, Jason Coppens, Len Shimoon, Rolf Meier, Bernard Bosi, David Kwong, Mark A. Gustlin
  • Patent number: 8649398
    Abstract: A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Farhad Shafai, Jason Coppens
  • Patent number: 8443256
    Abstract: A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial portion of the message fills n complete segments, where n<N. The method further includes processing the initial portion of the message placed on the bus to compute a CRC while compensating for any data on the bus preceding the initial portion, and subsequently processing one or more following portions of the message placed on the bus to update the CRC. A final portion of the message is processed to update the CRC by separately processing complete segments that do not fill the bus and any bytes that do not completely fill the last segment.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: May 14, 2013
    Assignee: Xilinx, Inc.
    Inventors: Farhad Shafai, Kelvin Spencer, Jason Coppens
  • Publication number: 20120236878
    Abstract: A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 20, 2012
    Applicant: SARANCE TECHNOLOGIES INC.
    Inventors: Farhad Shafai, Jason Coppens
  • Publication number: 20120192044
    Abstract: A CRC (Cyclic Redundancy Check) code for a data message is created by placing an initial portion of the data message on a bus of width W bits consisting of an integral number N of segments of width S such that the initial portion of the message fills n complete segments, where n?N. A known bit pattern is placed on any segments preceding a start of the message as determined by a start indicator. A first intermediate CRC code is computed for the n segments of the initial portion by applying the W bits of the bus forming an input word to a CRC full processing circuit using a compensating constant to compensate for any known bit pattern preceding the initial portion of the message. Subsequent portions of the message width W are placed on the bus during subsequent bus cycles, and in each case a new first intermediate CRC code is computed on the W bits of the bus as input words using the current first intermediate CRC code as a seed input.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: SARANCE TECHNOLOGIES INC.
    Inventors: Farhad Shafai, Kelvin Spencer, Jason Coppens