Abstract: An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives.

Abstract: An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives.

Abstract: A method and system for providing format savings in data sectors. The method includes receiving a signal outputted from an analog-to-digital conversion circuit. The method further includes shifting a signal phase of the signal based at least upon a corrected phase at an output of a phase loop and a phase measured when the signal was digitally sampled by the analog-to-digital conversion circuit. The method also includes adjusting a gain of the signal based at least upon a current gain loop correction and a gain correction made when the signal was digitally sampled by the analog-to-digital conversion circuit. Additionally, the method includes adjusting the signal based at least upon an output of a current offset correction and an offset correction made when the signal was digitally sampled by the analog-to-digital conversion circuit. The method also includes outputting an adjusted signal to a sync mark detector.

Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.

Abstract: The disclosure is directed to a system and method of determining signal quality based upon at least one of: a comparison of energy content of the signal to a threshold energy content, a comparison of energy content of the fundamental harmonic of the signal to a specified percentage of the energy content of the signal, and a comparison of a difference between phase of the signal and a target phase to a threshold phase difference.

Abstract: The disclosure is directed to a system and method of determining signal quality based upon at least one of: a comparison of energy content of the signal to a threshold energy content, a comparison of energy content of the fundamental harmonic of the signal to a specified percentage of the energy content of the signal, and a comparison of a difference between phase of the signal and a target phase to a threshold phase difference.

Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.

Abstract: An apparatus comprises an alternating current coupling stage comprising a first filter configured to filter an analog signal to remove relatively low-frequency energy and read channel circuitry coupled to the alternating current coupling stage. The read channel circuitry comprises an analog-to-digital converter configured to convert the filtered analog signal to a digital signal, a detector configured to obtain a recovered signal using the digital signal, and a baseline correction module comprising a second filter and being configured to estimate a parameter of the first filter using a least mean squares algorithm based at least in part on the analog signal and an output of the second filter, adjust a parameter of the second filter based on the estimated parameter and add at least a portion of the removed relatively low-frequency energy to the digital signal by combining the output of the second filter and the digital signal.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.

Abstract: A method includes designating a first sampling phase for a signal captured from a magnetic storage medium, where the signal is representative of information stored by the magnetic storage medium. The method further includes capturing a first waveform associated with the signal at the first sampling phase. The method also includes designating a second sampling phase different from the first sampling phase for the signal. The method further includes capturing a second waveform associated with the signal at the second sampling phase. The method also includes interleaving the first waveform and the second waveform to form an oversampled waveform. The first waveform and the second waveform are captured at a rate at least substantially equal to a rate at which the information stored by the magnetic storage medium was written to the magnetic storage medium.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track.

Abstract: A circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.

Abstract: A Viterbi detector receives a signal that represents a binary sequence having groups of no more and no fewer than a predetermined number of consecutive bits each having a first logic level, where the groups are separated from each other by respective bits having a second logic level. The Viterbi detector recovers the binary sequence from the signal by calculating a respective path metric for each of no more than four possible states of the binary sequence, and determining a surviving path from the calculated path metrics, where the binary sequence lies along the surviving path. Or, the Viterbi detector recovers the binary sequence from the signal by calculating respective path metrics for possible states of the binary sequence, calculating multiple path metrics for no more than one of the possible states, and determining the surviving path from the calculated path metrics.